274 lines
8.5 KiB
C
274 lines
8.5 KiB
C
/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC_TIMERS_H
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#define _MEC_TIMERS_H
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#include <stdint.h>
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#include <stddef.h>
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/* Basic timers */
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/* Offset between instances of the Basic Timer blocks */
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#define MCHP_BTMR_INSTANCE_POS 5ul
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#define MCHP_BTMR_INSTANCE_OFS 0x20u
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/* Base frequency of all basic timers is AHB clock */
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#define MCHP_BTMR_BASE_FREQ 48000000u
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#define MCHP_BTMR_MIN_FREQ (MCHP_BTMR_BASE_FREQ / 0x10000u)
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/*
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* Basic Timer Count Register (Offset +00h)
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* 32-bit R/W
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* 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
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*/
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#define MCHP_BTMR_CNT_OFS 0x00u
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/*
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* Basic Timer Preload Register (Offset +04h)
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* 32-bit R/W
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* 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
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*/
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#define MCHP_BTMR_PRELOAD_OFS 0x04u
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/* Basic Timer Status Register (Offset +08h) R/W1C */
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#define MCHP_BTMR_STS_OFS 0x08u
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#define MCHP_BTMR_STS_MASK 0x01u
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#define MCHP_BTMR_STS_ACTIVE_POS 0
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#define MCHP_BTMR_STS_ACTIVE 0x01u
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/* Basic Timer Interrupt Enable Register (Offset +0Ch) */
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#define MCHP_BTMR_INTEN_OFS 0x0cu
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#define MCHP_BTMR_INTEN_MASK 0x01u
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#define MCHP_BTMR_INTEN_POS 0
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#define MCHP_BTMR_INTEN 0x01u
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#define MCHP_BTMR_INTDIS 0u
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/* Basic Timer Control Register (Offset +10h) */
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#define MCHP_BTMR_CTRL_OFS 0x10u
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#define MCHP_BTMR_CTRL_MASK 0xffff00fdu
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#define MCHP_BTMR_CTRL_PRESCALE_POS 16u
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#define MCHP_BTMR_CTRL_PRESCALE_MASK0 0xffffu
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#define MCHP_BTMR_CTRL_PRESCALE_MASK 0xffff0000u
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#define MCHP_BTMR_CTRL_HALT 0x80u
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#define MCHP_BTMR_CTRL_RELOAD 0x40u
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#define MCHP_BTMR_CTRL_START 0x20u
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#define MCHP_BTMR_CTRL_SOFT_RESET 0x10u
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#define MCHP_BTMR_CTRL_AUTO_RESTART 0x08u
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#define MCHP_BTMR_CTRL_COUNT_UP 0x04u
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#define MCHP_BTMR_CTRL_ENABLE 0x01u
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/* */
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#define MCHP_BTMR_CTRL_HALT_POS 7u
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#define MCHP_BTMR_CTRL_RELOAD_POS 6u
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#define MCHP_BTMR_CTRL_START_POS 5u
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#define MCHP_BTMR_CTRL_SRESET_POS 4u
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#define MCHP_BTMR_CTRL_AUTO_RESTART_POS 3u
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#define MCHP_BTMR_CTRL_COUNT_DIR_POS 2u
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#define MCHP_BTMR_CTRL_ENABLE_POS 0u
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/** @brief Basic Timer(32 and 16 bit) registers. Total size = 20(0x14) bytes */
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struct btmr_regs {
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volatile uint32_t CNT;
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volatile uint32_t PRLD;
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volatile uint8_t STS;
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uint8_t RSVDC[3];
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volatile uint8_t IEN;
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uint8_t RSVDD[3];
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volatile uint32_t CTRL;
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};
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/*
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* Hibernation Timer
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* Set count resolution in bit[0]
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* 0 = 30.5 us (32786 Hz)
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* 1 = 125 ms (8 Hz)
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*/
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#define MCHP_HTMR_CTRL_REG_MASK 0x01u
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#define MCHP_HTMR_CTRL_RESOL_POS 0u
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#define MCHP_HTMR_CTRL_RESOL_MASK BIT(MCHP_HTMR_CTRL_EN_POS)
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#define MCHP_HTMR_CTRL_RESOL_30US 0u
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#define MCHP_HTMR_CTRL_RESOL_125MS BIT(MCHP_HTMR_CTRL_EN_POS)
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/*
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* Hibernation timer is started and stopped by writing a value
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* to the CNT (count) register.
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* Writing a non-zero value resets and start the counter counting down.
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* Writing 0 stops the timer.
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*/
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#define MCHP_HTMR_CNT_STOP_VALUE 0
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/** @brief Hibernation Timer (HTMR) */
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struct htmr_regs {
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volatile uint16_t PRLD;
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uint16_t RSVD1[1];
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volatile uint16_t CTRL;
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uint16_t RSVD2[1];
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volatile uint16_t CNT;
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uint16_t RSVD3[1];
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};
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/* Capture/Compare Timer */
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/* Control register at offset 0x00. Must use 32-bit access */
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#define MCHP_CCT_CTRL_ACTIVATE BIT(0)
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#define MCHP_CCT_CTRL_FRUN_EN BIT(1)
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#define MCHP_CCT_CTRL_FRUN_RESET BIT(2) /* self clearing bit */
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#define MCHP_CCT_CTRL_TCLK_MASK0 0x07u
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#define MCHP_CCT_CTRL_TCLK_MASK SHLU32(MCHP_CCT_CTRL_TCLK_MASK0, 4)
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#define MCHP_CCT_CTRL_TCLK_DIV_1 0u
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#define MCHP_CCT_CTRL_TCLK_DIV_2 SHLU32(1, 4)
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#define MCHP_CCT_CTRL_TCLK_DIV_4 SHLU32(2, 4)
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#define MCHP_CCT_CTRL_TCLK_DIV_8 SHLU32(3, 4)
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#define MCHP_CCT_CTRL_TCLK_DIV_16 SHLU32(4, 4)
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#define MCHP_CCT_CTRL_TCLK_DIV_32 SHLU32(5, 4)
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#define MCHP_CCT_CTRL_TCLK_DIV_64 SHLU32(6, 4)
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#define MCHP_CCT_CTRL_TCLK_DIV_128 SHLU32(7, 4)
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#define MCHP_CCT_CTRL_COMP0_EN BIT(8)
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#define MCHP_CCT_CTRL_COMP1_EN BIT(9)
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#define MCHP_CCT_CTRL_COMP1_SET BIT(16) /* R/WS */
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#define MCHP_CCT_CTRL_COMP0_SET BIT(17) /* R/WS */
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#define MCHP_CCT_CTRL_COMP1_CLR BIT(24) /* R/W1C */
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#define MCHP_CCT_CTRL_COMP0_CLR BIT(25) /* R/W1C */
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/** @brief Capture/Compare Timer */
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struct cct_regs {
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volatile uint32_t CTRL;
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volatile uint32_t CAP0_CTRL;
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volatile uint32_t CAP1_CTRL;
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volatile uint32_t FREE_RUN;
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volatile uint32_t CAP0;
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volatile uint32_t CAP1;
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volatile uint32_t CAP2;
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volatile uint32_t CAP3;
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volatile uint32_t CAP4;
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volatile uint32_t CAP5;
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volatile uint32_t COMP0;
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volatile uint32_t COMP1;
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};
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/* RTOS Timer */
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#define MCHP_RTMR_FREQ_HZ 32768u
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#define MCHP_RTMR_CTRL_MASK 0x1fu
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#define MCHP_RTMR_CTRL_BLK_EN_POS 0
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#define MCHP_RTMR_CTRL_BLK_EN_MASK BIT(MCHP_RTMR_CTRL_BLK_EN_POS)
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#define MCHP_RTMR_CTRL_BLK_EN BIT(MCHP_RTMR_CTRL_BLK_EN_POS)
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#define MCHP_RTMR_CTRL_AUTO_RELOAD_POS 1u
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#define MCHP_RTMR_CTRL_AUTO_RELOAD_MASK BIT(MCHP_RTMR_CTRL_AUTO_RELOAD_POS)
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#define MCHP_RTMR_CTRL_AUTO_RELOAD BIT(MCHP_RTMR_CTRL_AUTO_RELOAD_POS)
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#define MCHP_RTMR_CTRL_START_POS 2u
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#define MCHP_RTMR_CTRL_START_MASK BIT(MCHP_RTMR_CTRL_START_POS)
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#define MCHP_RTMR_CTRL_START BIT(MCHP_RTMR_CTRL_START_POS)
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#define MCHP_RTMR_CTRL_HW_HALT_EN_POS 3u
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#define MCHP_RTMR_CTRL_HW_HALT_EN_MASK BIT(MCHP_RTMR_CTRL_HW_HALT_EN_POS)
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#define MCHP_RTMR_CTRL_HW_HALT_EN BIT(MCHP_RTMR_CTRL_HW_HALT_EN_POS)
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#define MCHP_RTMR_CTRL_FW_HALT_EN_POS 4u
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#define MCHP_RTMR_CTRL_FW_HALT_EN_MASK BIT(MCHP_RTMR_CTRL_FW_HALT_EN_POS)
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#define MCHP_RTMR_CTRL_FW_HALT_EN BIT(MCHP_RTMR_CTRL_FW_HALT_EN_POS)
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/** @brief RTOS Timer (RTMR) */
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struct rtmr_regs {
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volatile uint32_t CNT;
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volatile uint32_t PRLD;
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volatile uint32_t CTRL;
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volatile uint32_t SOFTIRQ;
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};
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/* Week Timer */
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#define MCHP_WKTMR_CTRL_MASK 0x41u
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#define MCHP_WKTMR_CTRL_WT_EN_POS 0
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#define MCHP_WKTMR_CTRL_WT_EN_MASK BIT(MCHP_WKTMR_CTRL_WT_EN_POS)
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#define MCHP_WKTMR_CTRL_WT_EN BIT(MCHP_WKTMR_CTRL_WT_EN_POS)
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#define MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS 6u
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#define MCHP_WKTMR_CTRL_PWRUP_EV_EN_MASK BIT(MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS)
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#define MCHP_WKTMR_CTRL_PWRUP_EV_EN BIT(MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS)
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#define MCHP_WKTMR_ALARM_CNT_MASK 0x0fffffffu
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#define MCHP_WKTMR_TMR_CMP_MASK 0x0fffffffu
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#define MCHP_WKTMR_CLK_DIV_MASK 0x7fffu
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/* Sub-second interrupt select at +0x10 */
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#define MCHP_WKTMR_SS_MASK 0x0fu
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#define MCHP_WKTMR_SS_RATE_DIS 0x00u
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#define MCHP_WKTMR_SS_RATE_2HZ 0x01u
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#define MCHP_WKTMR_SS_RATE_4HZ 0x02u
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#define MCHP_WKTMR_SS_RATE_8HZ 0x03u
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#define MCHP_WKTMR_SS_RATE_16HZ 0x04u
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#define MCHP_WKTMR_SS_RATE_32HZ 0x05u
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#define MCHP_WKTMR_SS_RATE_64HZ 0x06u
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#define MCHP_WKTMR_SS_RATE_128HZ 0x07u
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#define MCHP_WKTMR_SS_RATE_256HZ 0x08u
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#define MCHP_WKTMR_SS_RATE_512HZ 0x09u
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#define MCHP_WKTMR_SS_RATE_1024HZ 0x0au
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#define MCHP_WKTMR_SS_RATE_2048HZ 0x0bu
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#define MCHP_WKTMR_SS_RATE_4096HZ 0x0cu
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#define MCHP_WKTMR_SS_RATE_8192HZ 0x0du
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#define MCHP_WKTMR_SS_RATE_16384HZ 0x0eu
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#define MCHP_WKTMR_SS_RATE_32768HZ 0x0fu
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/* Sub-week control at +0x14 */
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#define MCHP_WKTMR_SWKC_MASK 0x3f3u
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#define MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS 0ul
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#define MCHP_WKTMR_SWKC_PWRUP_EV_STS_MASK \
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BIT(MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS)
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#define MCHP_WKTMR_SWKC_PWRUP_EV_STS \
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BIT(MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS)
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#define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS 4
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#define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_MASK \
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BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS)
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#define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS \
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BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS)
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#define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS 5
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#define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_MASK \
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BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS)
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#define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN \
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BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS)
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#define MCHP_WKTMR_SWKC_AUTO_RELOAD_POS 6
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#define MCHP_WKTMR_SWKC_AUTO_RELOAD_MASK \
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BIT(MCHP_WKTMR_SWKC_AUTO_RELOAD_POS)
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#define MCHP_WKTMR_SWKC_AUTO_RELOAD \
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BIT(MCHP_WKTMR_SWKC_AUTO_RELOAD_POS)
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/* Sub-week alarm counter at +0x18 */
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#define MCHP_WKTMR_SWAC_MASK 0x1ff01ffu
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#define MCHP_WKTMR_SWAC_LOAD_POS 0
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#define MCHP_WKTMR_SWAC_CNT_RO_POS 16
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#define MCHP_WKTMR_SWAC_LOAD_MASK GENMASK(8, 0)
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#define MCHP_WKTMR_SWAC_CNT_RO_MASK GENMASK(24, 16)
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/* Week timer BGPO Data at +0x1c */
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#define MCHP_WKTMR_BGPO_DATA_MASK GENMASK(5, 0)
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/* Week timer BGPO Power at +0x20 */
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#define MCHP_WKTMR_BGPO_PWR_MASK GENMASK(5, 0)
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#define MCHP_WKTMR_BGPO_0_PWR_RO BIT(0)
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/* Week timer BGPO Reset at +0x24 */
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#define MCHP_WKTMR_BGPO_RST_MASK GENMASK(5, 0)
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#define MCHP_WKTMR_BGPO_RST_VBAT(n) BIT(n)
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/** @brief Week Timer (WKTMR) */
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struct wktmr_regs {
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volatile uint32_t CTRL;
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volatile uint32_t ALARM_CNT;
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volatile uint32_t TMR_CMP;
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volatile uint32_t CLKDIV;
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volatile uint32_t SUBSEC_ISEL;
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volatile uint32_t SUBWK_CTRL;
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volatile uint32_t SUBWK_ALARM_CNT;
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volatile uint32_t BGPO_DATA;
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volatile uint32_t BGPO_PWR;
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volatile uint32_t BGPO_RST;
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};
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#endif /* #ifndef _MEC_TIMERS_H */
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