103 lines
3.1 KiB
C
103 lines
3.1 KiB
C
/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC_GLOBAL_CFG_H
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#define _MEC_GLOBAL_CFG_H
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#include <stdint.h>
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#include <stddef.h>
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/*
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* Device and Revision ID 32-bit register
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* b[7:0] = Revision
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* b[15:8] = Device Sub-ID
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* b[31:16] = Device ID
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* This register can be accesses as bytes or a single 32-bit read from
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* the EC. Host access byte access via the Host visible configuration
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* register space at 0x2E/0x2F (default).
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*/
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#define MCHP_GCFG_DEV_ID_REG32_OFS 28u
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#define MCHP_GCFG_DEV_ID_REG_MASK GENMASK(31, 0)
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#define MCHP_GCFG_REV_ID_POS 0
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#define MCHP_GCFG_DID_REV_MASK GENMASK(7, 0)
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#define MCHP_GCFG_DID_SUB_ID_POS 8
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#define MCHP_GCFG_DID_SUB_ID_MASK GENMASK(15, 8)
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#define MCHP_GCFG_DID_DEV_ID_POS 16
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#define MCHP_GCFG_DID_DEV_ID_MASK GENMASK(31, 16)
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/* Byte[0] at offset 0x1c is the 8-bit revision ID */
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#define MCHP_GCFG_REV_A1 2u
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#define MCHP_GCFG_REV_B0 3u
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/*
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* Byte[1] at offset 0x1D is the 8-bit Sub-ID
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* bits[3:0] = package type
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* bits[7:4] = chip family
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*/
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#define MCHP_GCFG_SUB_ID_OFS 0x1du
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#define MCHP_GCFG_SUB_ID_PKG_POS 0
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#define MCHP_GCFG_SUB_ID_PKG_MASK GENMASK(3, 0)
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#define MCHP_GCFG_SUB_ID_PKG_UNDEF 0u
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#define MCHP_GCFG_SUB_ID_PKG_64_PIN 1u
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#define MCHP_GCFG_SUB_ID_PKG_84_PIN 2u
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#define MCHP_GCFG_SUB_ID_PKG_128_PIN 3u
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#define MCHP_GCFG_SUB_ID_PKG_144_PIN 4u
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#define MCHP_GCFG_SUB_ID_PKG_176_PIN 7u
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/* chip family field */
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#define MCHP_GCFG_SUB_ID_FAM_POS 4u
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#define MCHP_GCFG_SUB_ID_FAM_MASK GENMASK(7, 4)
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#define MCHP_GCFG_SUB_ID_FAM_UNDEF 0u
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#define MCHP_GCFG_SUB_ID_FAM_1 0x10u
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#define MCHP_GCFG_SUB_ID_FAM_2 0x20u
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#define MCHP_GCFG_SUB_ID_FAM_3 0x30u
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#define MCHP_GCFG_SUB_ID_FAM_4 0x40u
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#define MCHP_GCFG_SUB_ID_FAM_5 0x50u
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#define MCHP_GCFG_SUB_ID_FAM_6 0x60u
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#define MCHP_GCFG_SUB_ID_FAM_7 0x70u
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#define MCHP_GCFG_DEV_ID_LSB_OFS 0x1eu
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#define MCHP_GCFG_DEV_ID_MSB_OFS 0x1fu
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#define MCHP_GCFG_DEV_ID_172X 0x0022u
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#define MCHP_GCFG_DEV_ID_172X_LSB 0x22u
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#define MCHP_GCFG_DEV_ID_172X_MSB 0x00u
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/* SZ 144-pin package parts */
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#define MCHP_GCFG_DEVID_1723_144 0x00223400u
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#define MCHP_GCFG_DEVID_1727_144 0x00227400u
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/* LJ 176-pin package parts */
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#define MCHP_GCFG_DID_1721_176 0x00222700u
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#define MCHP_GCFG_DID_1723_176 0x00223700u
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#define MCHP_GCFG_DID_1727_176 0x00227700u
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/* Legacy Device ID value */
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#define MCHP_CCFG_LEGACY_DID_REG_OFS 0x20u
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#define MCHP_GCFG_LEGACY_DEV_ID 0xfeu
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/* Host access via configuration port (default I/O locations 0x2E/0x2F) */
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#define MCHP_HOST_CFG_INDEX_IO_DFLT 0x2eu
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#define MCHP_HOST_CFG_DATA_IO_DFLT 0x2fu
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#define MCHP_HOST_CFG_UNLOCK 0x55u
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#define MCHP_HOST_CFG_LOCK 0xaau
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/* Logical Device Configuration Indices */
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#define MCHP_HOST_CFG_LDN_IDX 7u
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#define MCHP_HOST_CFG_LD_ACTIVATE_IDX 0x30u
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#define MCHP_HOST_CFG_LD_BASE_ADDR_IDX 0x34u
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#define MCHP_HOST_CFG_LD_CFG_SEL_IDX 0xf0u
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/* Global Configuration Registers */
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struct global_cfg_regs {
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volatile uint8_t RSVD0[2];
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volatile uint8_t TEST02;
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volatile uint8_t RSVD1[4];
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volatile uint8_t LOG_DEV_NUM;
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volatile uint8_t RSVD2[20];
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volatile uint32_t DEV_REV_ID;
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volatile uint8_t LEGACY_DEV_ID;
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volatile uint8_t RSVD3[14];
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};
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#endif /* #ifndef _MEC_GLOBAL_CFG_H */
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