143 lines
4.9 KiB
C
143 lines
4.9 KiB
C
/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC_ADC_H
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#define _MEC_ADC_H
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#include <stdint.h>
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#include <stddef.h>
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/* Eight ADC channels numbered 0 - 7 */
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#define MCHP_ADC_MAX_CHAN 8u
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#define MCHP_ADC_MAX_CHAN_MASK 0x07u
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/* Control register */
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#define MCHP_ADC_CTRL_REG_OFS 0u
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#define MCHP_ADC_CTRL_REG_MASK 0xdfu
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#define MCHP_ADC_CTRL_REG_RW_MASK 0x1fu
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#define MCHP_ADC_CTRL_REG_RW1C_MASK 0xc0u
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#define MCHP_ADC_CTRL_ACTV BIT(0)
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#define MCHP_ADC_CTRL_START_SNGL BIT(1)
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#define MCHP_ADC_CTRL_START_RPT BIT(2)
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#define MCHP_ADC_CTRL_PWRSV_DIS BIT(3)
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#define MCHP_ADC_CTRL_SRST BIT(4)
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#define MCHP_ADC_CTRL_RPT_DONE_STS BIT(6) /* R/W1C */
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#define MCHP_ADC_CTRL_SNGL_DONE_STS BIT(7) /* R/W1C */
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/* Delay register. Start and repeat delays in units of 40 us */
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#define MCHP_ADC_DELAY_REG_OFS 4u
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#define MCHP_ADC_DELAY_REG_MASK 0xffffffffu
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#define MCHP_ADC_DELAY_START_POS 0u
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#define MCHP_ADC_DELAY_START_MASK 0xffffu
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#define MCHP_ADC_DELAY_RPT_POS 16u
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#define MCHP_ADC_DELAY_RPT_MASK 0xffff0000u
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/* Status register. 0 <= n < MCHP_ADC_MAX_CHAN */
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#define MCHP_ADC_STATUS_REG_OFS 8u
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#define MCHP_ADC_STATUS_REG_MASK 0xffffu
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#define MCHP_ADC_STATUS_CHAN(n) BIT(n)
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/* Single Conversion Select register */
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#define MCHP_ADC_SCS_REG_OFS 0x0cu
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#define MCHP_ADC_SCS_REG_MASK 0xffu
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#define MCHP_ADC_SCS_CH_0_7 0xffu
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#define MCHP_ADC_SCS_CH(n) BIT(((n) & 0x07u))
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/* Repeat Conversion Select register */
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#define MCHP_ADC_RCS_REG_OFS 0x10u
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#define MCHP_ADC_RCS_REG_MASK 0xffu
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#define MCHP_ADC_RCS_CH_0_7 0xffu
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#define MCHP_ADC_RCS_CH(n) BIT(((n) & 0x07u))
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/* Channel reading registers */
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#define MCHP_ADC_RDCH_REG_MASK 0xfffu
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#define MCHP_ADC_RDCH0_REG_OFS 0x14u
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#define MCHP_ADC_RDCH1_REG_OFS 0x18u
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#define MCHP_ADC_RDCH2_REG_OFS 0x1cu
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#define MCHP_ADC_RDCH3_REG_OFS 0x20u
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#define MCHP_ADC_RDCH4_REG_OFS 0x24u
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#define MCHP_ADC_RDCH5_REG_OFS 0x28u
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#define MCHP_ADC_RDCH6_REG_OFS 0x2cu
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#define MCHP_ADC_RDCH7_REG_OFS 0x30u
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/* Configuration register */
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#define MCHP_ADC_CFG_REG_OFS 0x7cu
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#define MCHP_ADC_CFG_REG_MASK 0xffffu
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#define MCHP_ADC_CFG_CLK_LO_TIME_POS 0
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#define MCHP_ADC_CFG_CLK_LO_TIME_MASK0 0xffu
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#define MCHP_ADC_CFG_CLK_LO_TIME_MASK 0xffu
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#define MCHP_ADC_CFG_CLK_HI_TIME_POS 8
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#define MCHP_ADC_CFG_CLK_HI_TIME_MASK0 0xffu
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#define MCHP_ADC_CFG_CLK_HI_TIME_MASK SHLU32(0xffu, 8)
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/* Channel Vref Select register */
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#define MCHP_ADC_CH_VREF_SEL_REG_OFS 0x80u
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#define MCHP_ADC_CH_VREF_SEL_REG_MASK 0x00ffffffu
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#define MCHP_ADC_CH_VREF_SEL_MASK(n) SHLU32(0x03u, (((n) & 0x07) * 2u))
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#define MCHP_ADC_CH_VREF_SEL_PAD(n) 0u
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#define MCHP_ADC_CH_VREF_SEL_GPIO(n) SHLU32(0x01u, (((n) & 0x07) * 2u))
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/* Vref Control register */
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#define MCHP_ADC_VREF_CTRL_REG_OFS 0x84u
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#define MCHP_ADC_VREF_CTRL_REG_MASK 0xffffffffu
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#define MCHP_ADC_VREF_CTRL_CHRG_DEL_POS 0
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#define MCHP_ADC_VREF_CTRL_CHRG_DEL_MASK0 0xffffu
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#define MCHP_ADC_VREF_CTRL_CHRG_DEL_MASK 0xffffu
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#define MCHP_ADC_VREF_CTRL_SW_DEL_POS 16
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#define MCHP_ADC_VREF_CTRL_SW_DEL_MASK0 0x1fffu
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#define MCHP_ADC_VREF_CTRL_SW_DEL_MASK SHLU32(0x1fffu, 16)
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#define MCHP_ADC_VREF_CTRL_PAD_POS 29
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#define MCHP_ADC_VREF_CTRL_PAD_UNUSED_FLOAT 0u
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#define MCHP_ADC_VREF_CTRL_PAD_UNUSED_DRIVE_LO BIT(29)
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#define MCHP_ADC_VREF_CTRL_SEL_STS_POS 30
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#define MCHP_ADC_VREF_CTRL_SEL_STS_MASK0 0x03u
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#define MCHP_ADC_VREF_CTRL_SEL_STS_MASK SHLU32(3u, 30)
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/* SAR ADC Control register */
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#define MCHP_ADC_SAR_CTRL_REG_OFS 0x88u
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#define MCHP_ADC_SAR_CTRL_REG_MASK 0x0001ff8fu
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/* Select single ended or differential operation */
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#define MCHP_ADC_SAR_CTRL_SELDIFF_POS 0
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#define MCHP_ADC_SAR_CTRL_SELDIFF_DIS 0u
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#define MCHP_ADC_SAR_CTRL_SELDIFF_EN BIT(0)
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/* Select resolution */
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#define MCHP_ADC_SAR_CTRL_RES_POS 1
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#define MCHP_ADC_SAR_CTRL_RES_MASK0 0x03u
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#define MCHP_ADC_SAR_CTRL_RES_MASK 0x06u
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#define MCHP_ADC_SAR_CTRL_RES_10_BITS 0x04u
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#define MCHP_ADC_SAR_CTRL_RES_12_BITS 0x06u
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/* Shift data in reading register */
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#define MCHP_ADC_SAR_CTRL_SHIFTD_POS 3
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#define MCHP_ADC_SAR_CTRL_SHIFTD_DIS 0u
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#define MCHP_ADC_SAR_CTRL_SHIFTD_EN BIT(3)
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/* Warm up delay in ADC clock cycles */
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#define MCHP_ADC_SAR_CTRL_WUP_DLY_POS 7
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#define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK0 0x3ffu
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#define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK SHLU32(0x3ffu, 7)
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#define MCHP_ADC_SAR_CTRL_WUP_DLY_DFLT SHLU32(0x202u, 7)
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/* Register interface */
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#define MCHP_ADC_CH_NUM(n) ((n) & MCHP_ADC_MAX_CHAN_MASK)
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#define MCHP_ADC_CH_OFS(n) (MCHP_ADC_CH_NUM(n) * 4u)
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#define MCHP_ADC_CH_ADDR(n) (MCHP_ADC_BASE_ADDR + MCHP_ADC_CH_OFS(n))
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/** @brief Analog to Digital Converter Registers (ADC) */
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struct adc_regs {
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volatile uint32_t CONTROL;
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volatile uint32_t DELAY;
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volatile uint32_t STATUS;
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volatile uint32_t SINGLE;
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volatile uint32_t REPEAT;
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volatile uint32_t RD[8];
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uint8_t RSVD1[0x7c - 0x34];
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volatile uint32_t CONFIG;
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volatile uint32_t VREF_CHAN_SEL;
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volatile uint32_t VREF_CTRL;
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volatile uint32_t SARADC_CTRL;
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};
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#endif /* #ifndef _MEC_ADC_H */
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