zephyr/arch/arm
Jaxson Han a7a8a64e9c arch32: Fix incorrect exc_exit sequence
The incorrect sequence will cause the thread cannot be aborted in the
ISR context. The following test case failed:
tests/kernel/fatal/exception/kernel.common.stack_sentinel.

The stack sentinel detects the stack overflow as normal during a timer
ISR exit. Note that, currently, the stack overflow detection is behind
the context switch checking, and then the detection will call svc to
raise a fatal error resulting in increasing the nested counter(+1). At
this point, it needs a context switch to finally abort the thread.
However, after the fatal error handling, the program cannot do a context
switch either during the svc exit[1], or during the timer ISR exit[2].

[1] is because the svc context is in an interrupt nested state (the
nested counter is 2).
[2] is because the current point (after svc context pop out) is right
behind the switch checking.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2022-03-21 07:31:29 -04:00
..
core arch32: Fix incorrect exc_exit sequence 2022-03-21 07:31:29 -04:00
include arch: arm: aarch32: Change CPU_CORTEX_R kconfig option 2022-02-23 08:14:15 -06:00
CMakeLists.txt arm/arm64: Make ARM64 a standalone architecture 2021-03-31 10:34:33 -05:00
Kconfig Kconfig: Add a new config CODE_DATA_RELOCATION_SRAM 2021-05-04 15:46:52 +02:00