602 lines
17 KiB
C
602 lines
17 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_xec_gpio
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#include <errno.h>
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#include <device.h>
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#include <drivers/gpio.h>
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#include <soc.h>
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#include "gpio_utils.h"
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#define GPIO_IN_BASE(config) \
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((__IO uint32_t *)(GPIO_PARIN_BASE + (config->port_num << 2)))
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#define GPIO_OUT_BASE(config) \
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((__IO uint32_t *)(GPIO_PAROUT_BASE + (config->port_num << 2)))
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static const uint32_t valid_ctrl_masks[NUM_MCHP_GPIO_PORTS] = {
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(MCHP_GPIO_PORT_A_BITMAP),
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(MCHP_GPIO_PORT_B_BITMAP),
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(MCHP_GPIO_PORT_C_BITMAP),
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(MCHP_GPIO_PORT_D_BITMAP),
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(MCHP_GPIO_PORT_E_BITMAP),
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(MCHP_GPIO_PORT_F_BITMAP)
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};
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struct gpio_xec_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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};
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struct gpio_xec_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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__IO uint32_t *pcr1_base;
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uint8_t girq_id;
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uint32_t port_num;
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uint32_t flags;
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};
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/*
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* notes: The GPIO parallel output bits are read-only until the
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* Alternate-Output-Disable (AOD) bit is set in the pin's control
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* register. To preload a parallel output value to prevent certain
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* classes of glitching for output pins we must:
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* Set GPIO control AOD=1 with the pin direction set to input.
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* Program the new pin value in the respective GPIO parallel output
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* register.
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* Program other GPIO control bits except direction.
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* Last step set the GPIO control register direction bit to output.
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*/
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static int gpio_xec_configure(const struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_xec_config *config = dev->config;
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__IO uint32_t *current_pcr1;
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uint32_t pcr1 = 0U;
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uint32_t mask = 0U;
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__IO uint32_t *gpio_out_reg = GPIO_OUT_BASE(config);
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/* Validate pin number range in terms of current port */
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if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0U) {
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return -EINVAL;
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}
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/* Don't support "open source" mode */
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if (((flags & GPIO_SINGLE_ENDED) != 0U) &&
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((flags & GPIO_LINE_OPEN_DRAIN) == 0U)) {
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return -ENOTSUP;
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}
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/* The flags contain options that require touching registers in the
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* PCRs for a given GPIO. There are no GPIO modules in Microchip SOCs!
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* Keep direction as input until last.
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* Clear input pad disable allowing input pad to operate.
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* Clear Power gate to allow pads to operate.
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*/
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mask |= MCHP_GPIO_CTRL_DIR_MASK;
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mask |= MCHP_GPIO_CTRL_INPAD_DIS_MASK;
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mask |= MCHP_GPIO_CTRL_PWRG_MASK;
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pcr1 |= MCHP_GPIO_CTRL_DIR_INPUT;
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/* Figure out the pullup/pulldown configuration and keep it in the
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* pcr1 variable
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*/
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mask |= MCHP_GPIO_CTRL_PUD_MASK;
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if ((flags & GPIO_PULL_UP) != 0U) {
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/* Enable the pull and select the pullup resistor. */
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pcr1 |= MCHP_GPIO_CTRL_PUD_PU;
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} else if ((flags & GPIO_PULL_DOWN) != 0U) {
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/* Enable the pull and select the pulldown resistor */
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pcr1 |= MCHP_GPIO_CTRL_PUD_PD;
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}
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/* Push-pull or open drain */
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mask |= MCHP_GPIO_CTRL_BUFT_MASK;
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if ((flags & GPIO_OPEN_DRAIN) != 0U) {
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/* Open drain */
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pcr1 |= MCHP_GPIO_CTRL_BUFT_OPENDRAIN;
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} else {
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/* Push-pull */
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pcr1 |= MCHP_GPIO_CTRL_BUFT_PUSHPULL;
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}
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/* Use GPIO output register to control pin output, instead of
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* using the control register (=> alternate output disable).
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*/
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mask |= MCHP_GPIO_CTRL_AOD_MASK;
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pcr1 |= MCHP_GPIO_CTRL_AOD_DIS;
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/* Make sure disconnected on first control register write */
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if (flags == GPIO_DISCONNECTED) {
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pcr1 |= MCHP_GPIO_CTRL_PWRG_OFF;
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}
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/* Now write contents of pcr1 variable to the PCR1 register that
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* corresponds to the GPIO being configured.
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* AOD is 1 and direction is input. HW will allow use to set the
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* GPIO parallel output bit for this pin and with the pin direction
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* as input no glitch will occur.
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*/
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current_pcr1 = config->pcr1_base + pin;
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*current_pcr1 = (*current_pcr1 & ~mask) | pcr1;
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if ((flags & GPIO_OUTPUT) != 0U) {
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
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*gpio_out_reg |= BIT(pin);
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
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*gpio_out_reg &= ~BIT(pin);
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}
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mask = MCHP_GPIO_CTRL_DIR_MASK;
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pcr1 = MCHP_GPIO_CTRL_DIR_OUTPUT;
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*current_pcr1 = (*current_pcr1 & ~mask) | pcr1;
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}
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return 0;
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}
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static int gpio_xec_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_xec_config *config = dev->config;
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__IO uint32_t *current_pcr1;
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uint32_t pcr1 = 0U;
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uint32_t mask = 0U;
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uint32_t gpio_interrupt = 0U;
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/* Validate pin number range in terms of current port */
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if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0U) {
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return -EINVAL;
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}
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/* Check if GPIO port supports interrupts */
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if ((mode != GPIO_INT_MODE_DISABLED) &&
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((config->flags & GPIO_INT_ENABLE) == 0U)) {
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return -ENOTSUP;
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}
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/* Disable interrupt in the EC aggregator */
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MCHP_GIRQ_ENCLR(config->girq_id) = BIT(pin);
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/* Assemble mask for level/edge triggered interrrupts */
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mask |= MCHP_GPIO_CTRL_IDET_MASK;
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if (mode == GPIO_INT_MODE_DISABLED) {
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/* Explicitly disable interrupts, otherwise the configuration
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* results in level triggered/low interrupts
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*/
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pcr1 |= MCHP_GPIO_CTRL_IDET_DISABLE;
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} else {
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if (mode == GPIO_INT_MODE_LEVEL) {
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/* Enable level interrupts */
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if (trig == GPIO_INT_TRIG_HIGH) {
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gpio_interrupt = MCHP_GPIO_CTRL_IDET_LVL_HI;
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} else {
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gpio_interrupt = MCHP_GPIO_CTRL_IDET_LVL_LO;
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}
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} else {
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/* Enable edge interrupts */
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switch (trig) {
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case GPIO_INT_TRIG_LOW:
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gpio_interrupt = MCHP_GPIO_CTRL_IDET_FEDGE;
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break;
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case GPIO_INT_TRIG_HIGH:
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gpio_interrupt = MCHP_GPIO_CTRL_IDET_REDGE;
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break;
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case GPIO_INT_TRIG_BOTH:
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gpio_interrupt = MCHP_GPIO_CTRL_IDET_BEDGE;
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break;
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default:
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return -EINVAL;
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}
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}
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pcr1 |= gpio_interrupt;
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}
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/* Now write contents of pcr1 variable to the PCR1 register that
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* corresponds to the GPIO being configured
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*/
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current_pcr1 = config->pcr1_base + pin;
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*current_pcr1 = (*current_pcr1 & ~mask) | pcr1;
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if (mode != GPIO_INT_MODE_DISABLED) {
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/* We enable the interrupts in the EC aggregator so that the
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* result can be forwarded to the ARM NVIC
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*/
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MCHP_GIRQ_SRC_CLR(config->girq_id, pin);
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MCHP_GIRQ_ENSET(config->girq_id) = BIT(pin);
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}
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return 0;
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}
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static int gpio_xec_port_set_masked_raw(const struct device *dev,
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uint32_t mask,
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uint32_t value)
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{
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const struct gpio_xec_config *config = dev->config;
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/* GPIO output registers are used for writing */
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__IO uint32_t *gpio_base = GPIO_OUT_BASE(config);
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*gpio_base = (*gpio_base & ~mask) | (mask & value);
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return 0;
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}
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static int gpio_xec_port_set_bits_raw(const struct device *dev, uint32_t mask)
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{
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const struct gpio_xec_config *config = dev->config;
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/* GPIO output registers are used for writing */
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__IO uint32_t *gpio_base = GPIO_OUT_BASE(config);
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*gpio_base |= mask;
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return 0;
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}
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static int gpio_xec_port_clear_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_xec_config *config = dev->config;
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/* GPIO output registers are used for writing */
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__IO uint32_t *gpio_base = GPIO_OUT_BASE(config);
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*gpio_base &= ~mask;
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return 0;
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}
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static int gpio_xec_port_toggle_bits(const struct device *dev, uint32_t mask)
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{
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const struct gpio_xec_config *config = dev->config;
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/* GPIO output registers are used for writing */
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__IO uint32_t *gpio_base = GPIO_OUT_BASE(config);
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*gpio_base ^= mask;
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return 0;
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}
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static int gpio_xec_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_xec_config *config = dev->config;
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/* GPIO input registers are used for reading */
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__IO uint32_t *gpio_base = GPIO_IN_BASE(config);
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*value = *gpio_base;
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return 0;
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}
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static int gpio_xec_manage_callback(const struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_xec_data *data = dev->data;
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gpio_manage_callback(&data->callbacks, callback, set);
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return 0;
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}
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static void gpio_gpio_xec_port_isr(const struct device *dev)
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{
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const struct gpio_xec_config *config = dev->config;
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struct gpio_xec_data *data = dev->data;
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uint32_t girq_result;
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/* Figure out which interrupts have been triggered from the EC
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* aggregator result register
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*/
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girq_result = MCHP_GIRQ_RESULT(config->girq_id);
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/* Clear source register in aggregator before firing callbacks */
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REG32(MCHP_GIRQ_SRC_ADDR(config->girq_id)) = girq_result;
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gpio_fire_callbacks(&data->callbacks, dev, girq_result);
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}
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static const struct gpio_driver_api gpio_xec_driver_api = {
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.pin_configure = gpio_xec_configure,
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.port_get_raw = gpio_xec_port_get_raw,
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.port_set_masked_raw = gpio_xec_port_set_masked_raw,
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.port_set_bits_raw = gpio_xec_port_set_bits_raw,
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.port_clear_bits_raw = gpio_xec_port_clear_bits_raw,
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.port_toggle_bits = gpio_xec_port_toggle_bits,
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.pin_interrupt_configure = gpio_xec_pin_interrupt_configure,
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.manage_callback = gpio_xec_manage_callback,
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};
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_000_036), okay)
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static int gpio_xec_port000_036_init(const struct device *dev);
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static const struct gpio_xec_config gpio_xec_port000_036_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(
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DT_NODELABEL(gpio_000_036)),
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},
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.pcr1_base = (uint32_t *) DT_REG_ADDR(DT_NODELABEL(gpio_000_036)),
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.port_num = MCHP_GPIO_000_036,
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#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_000_036), irq)
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.girq_id = MCHP_GIRQ11_ID,
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.flags = GPIO_INT_ENABLE,
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#else
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.flags = 0,
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#endif
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};
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static struct gpio_xec_data gpio_xec_port000_036_data;
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DEVICE_DT_DEFINE(DT_NODELABEL(gpio_000_036),
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gpio_xec_port000_036_init,
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NULL,
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&gpio_xec_port000_036_data, &gpio_xec_port000_036_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_xec_driver_api);
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static int gpio_xec_port000_036_init(const struct device *dev)
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{
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#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_000_036), irq)
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const struct gpio_xec_config *config = dev->config;
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/* Turn on the block enable in the EC aggregator */
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MCHP_GIRQ_BLK_SETEN(config->girq_id);
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IRQ_CONNECT(DT_IRQ(DT_NODELABEL(gpio_000_036), irq),
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DT_IRQ(DT_NODELABEL(gpio_000_036), priority),
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gpio_gpio_xec_port_isr,
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DEVICE_DT_GET(DT_NODELABEL(gpio_000_036)), 0U);
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irq_enable(DT_IRQ(DT_NODELABEL(gpio_000_036), irq));
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#endif
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return 0;
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}
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_000_036), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_040_076), okay)
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static int gpio_xec_port040_076_init(const struct device *dev);
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static const struct gpio_xec_config gpio_xec_port040_076_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(
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DT_NODELABEL(gpio_040_076)),
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},
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.pcr1_base = (uint32_t *) DT_REG_ADDR(DT_NODELABEL(gpio_040_076)),
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.port_num = MCHP_GPIO_040_076,
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#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_040_076), irq)
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.girq_id = MCHP_GIRQ10_ID,
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.flags = GPIO_INT_ENABLE,
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#else
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.flags = 0,
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#endif
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};
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static struct gpio_xec_data gpio_xec_port040_076_data;
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DEVICE_DT_DEFINE(DT_NODELABEL(gpio_040_076),
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gpio_xec_port040_076_init,
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NULL,
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&gpio_xec_port040_076_data, &gpio_xec_port040_076_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_xec_driver_api);
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static int gpio_xec_port040_076_init(const struct device *dev)
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{
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#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_040_076), irq)
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const struct gpio_xec_config *config = dev->config;
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/* Turn on the block enable in the EC aggregator */
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MCHP_GIRQ_BLK_SETEN(config->girq_id);
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IRQ_CONNECT(DT_IRQ(DT_NODELABEL(gpio_040_076), irq),
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DT_IRQ(DT_NODELABEL(gpio_040_076), priority),
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gpio_gpio_xec_port_isr,
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DEVICE_DT_GET(DT_NODELABEL(gpio_040_076)), 0U);
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irq_enable(DT_IRQ(DT_NODELABEL(gpio_040_076), irq));
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#endif
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return 0;
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}
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_040_076), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_100_136), okay)
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static int gpio_xec_port100_136_init(const struct device *dev);
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static const struct gpio_xec_config gpio_xec_port100_136_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(
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DT_NODELABEL(gpio_100_136)),
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},
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.pcr1_base = (uint32_t *) DT_REG_ADDR(DT_NODELABEL(gpio_100_136)),
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.port_num = MCHP_GPIO_100_136,
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#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_100_136), irq)
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.girq_id = MCHP_GIRQ09_ID,
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.flags = GPIO_INT_ENABLE,
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#else
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.flags = 0,
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#endif
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};
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static struct gpio_xec_data gpio_xec_port100_136_data;
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DEVICE_DT_DEFINE(DT_NODELABEL(gpio_100_136),
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gpio_xec_port100_136_init,
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NULL,
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&gpio_xec_port100_136_data, &gpio_xec_port100_136_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_xec_driver_api);
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static int gpio_xec_port100_136_init(const struct device *dev)
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{
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#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_100_136), irq)
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const struct gpio_xec_config *config = dev->config;
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/* Turn on the block enable in the EC aggregator */
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MCHP_GIRQ_BLK_SETEN(config->girq_id);
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IRQ_CONNECT(DT_IRQ(DT_NODELABEL(gpio_100_136), irq),
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DT_IRQ(DT_NODELABEL(gpio_100_136), priority),
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gpio_gpio_xec_port_isr,
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DEVICE_DT_GET(DT_NODELABEL(gpio_100_136)), 0U);
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irq_enable(DT_IRQ(DT_NODELABEL(gpio_100_136), irq));
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#endif
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return 0;
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}
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_100_136), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_140_176), okay)
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static int gpio_xec_port140_176_init(const struct device *dev);
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static const struct gpio_xec_config gpio_xec_port140_176_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(
|
|
DT_NODELABEL(gpio_140_176)),
|
|
},
|
|
.pcr1_base = (uint32_t *) DT_REG_ADDR(DT_NODELABEL(gpio_140_176)),
|
|
.port_num = MCHP_GPIO_140_176,
|
|
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_140_176), irq)
|
|
.girq_id = MCHP_GIRQ08_ID,
|
|
.flags = GPIO_INT_ENABLE,
|
|
#else
|
|
.flags = 0,
|
|
#endif
|
|
};
|
|
|
|
static struct gpio_xec_data gpio_xec_port140_176_data;
|
|
|
|
DEVICE_DT_DEFINE(DT_NODELABEL(gpio_140_176),
|
|
gpio_xec_port140_176_init,
|
|
NULL,
|
|
&gpio_xec_port140_176_data, &gpio_xec_port140_176_config,
|
|
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
|
&gpio_xec_driver_api);
|
|
|
|
static int gpio_xec_port140_176_init(const struct device *dev)
|
|
{
|
|
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_140_176), irq)
|
|
const struct gpio_xec_config *config = dev->config;
|
|
|
|
/* Turn on the block enable in the EC aggregator */
|
|
MCHP_GIRQ_BLK_SETEN(config->girq_id);
|
|
|
|
IRQ_CONNECT(DT_IRQ(DT_NODELABEL(gpio_140_176), irq),
|
|
DT_IRQ(DT_NODELABEL(gpio_140_176), priority),
|
|
gpio_gpio_xec_port_isr,
|
|
DEVICE_DT_GET(DT_NODELABEL(gpio_140_176)), 0U);
|
|
|
|
irq_enable(DT_IRQ(DT_NODELABEL(gpio_140_176), irq));
|
|
#endif
|
|
return 0;
|
|
}
|
|
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_140_176), okay) */
|
|
|
|
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_200_236), okay)
|
|
static int gpio_xec_port200_236_init(const struct device *dev);
|
|
|
|
static const struct gpio_xec_config gpio_xec_port200_236_config = {
|
|
.common = {
|
|
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(
|
|
DT_NODELABEL(gpio_200_236)),
|
|
},
|
|
.pcr1_base = (uint32_t *) DT_REG_ADDR(DT_NODELABEL(gpio_200_236)),
|
|
.port_num = MCHP_GPIO_200_236,
|
|
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_200_236), irq)
|
|
.girq_id = MCHP_GIRQ12_ID,
|
|
.flags = GPIO_INT_ENABLE,
|
|
#else
|
|
.flags = 0,
|
|
#endif
|
|
};
|
|
|
|
static struct gpio_xec_data gpio_xec_port200_236_data;
|
|
|
|
DEVICE_DT_DEFINE(DT_NODELABEL(gpio_200_236),
|
|
gpio_xec_port200_236_init,
|
|
NULL,
|
|
&gpio_xec_port200_236_data, &gpio_xec_port200_236_config,
|
|
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
|
&gpio_xec_driver_api);
|
|
|
|
static int gpio_xec_port200_236_init(const struct device *dev)
|
|
{
|
|
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_200_236), irq)
|
|
const struct gpio_xec_config *config = dev->config;
|
|
|
|
/* Turn on the block enable in the EC aggregator */
|
|
MCHP_GIRQ_BLK_SETEN(config->girq_id);
|
|
|
|
IRQ_CONNECT(DT_IRQ(DT_NODELABEL(gpio_200_236), irq),
|
|
DT_IRQ(DT_NODELABEL(gpio_200_236), priority),
|
|
gpio_gpio_xec_port_isr,
|
|
DEVICE_DT_GET(DT_NODELABEL(gpio_200_236)), 0U);
|
|
|
|
irq_enable(DT_IRQ(DT_NODELABEL(gpio_200_236), irq));
|
|
#endif
|
|
return 0;
|
|
}
|
|
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_200_236), okay) */
|
|
|
|
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_240_276), okay)
|
|
static int gpio_xec_port240_276_init(const struct device *dev);
|
|
|
|
static const struct gpio_xec_config gpio_xec_port240_276_config = {
|
|
.common = {
|
|
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(
|
|
DT_NODELABEL(gpio_240_276)),
|
|
},
|
|
.pcr1_base = (uint32_t *) DT_REG_ADDR(DT_NODELABEL(gpio_240_276)),
|
|
.port_num = MCHP_GPIO_240_276,
|
|
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_240_276), irq)
|
|
.girq_id = MCHP_GIRQ26_ID,
|
|
.flags = GPIO_INT_ENABLE,
|
|
#else
|
|
.flags = 0,
|
|
#endif
|
|
};
|
|
|
|
static struct gpio_xec_data gpio_xec_port240_276_data;
|
|
|
|
DEVICE_DT_DEFINE(DT_NODELABEL(gpio_240_276),
|
|
gpio_xec_port240_276_init,
|
|
NULL,
|
|
&gpio_xec_port240_276_data, &gpio_xec_port240_276_config,
|
|
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
|
&gpio_xec_driver_api);
|
|
|
|
static int gpio_xec_port240_276_init(const struct device *dev)
|
|
{
|
|
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_240_276), irq)
|
|
const struct gpio_xec_config *config = dev->config;
|
|
|
|
/* Turn on the block enable in the EC aggregator */
|
|
MCHP_GIRQ_BLK_SETEN(config->girq_id);
|
|
|
|
IRQ_CONNECT(DT_IRQ(DT_NODELABEL(gpio_240_276), irq),
|
|
DT_IRQ(DT_NODELABEL(gpio_240_276), priority),
|
|
gpio_gpio_xec_port_isr,
|
|
DEVICE_DT_GET(DT_NODELABEL(gpio_240_276)), 0U);
|
|
|
|
irq_enable(DT_IRQ(DT_NODELABEL(gpio_240_276), irq));
|
|
#endif
|
|
return 0;
|
|
}
|
|
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_240_276), okay) */
|