708 lines
20 KiB
C
708 lines
20 KiB
C
/*
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* Copyright (c) 2018, Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/counter.h>
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#include <drivers/clock_control.h>
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#include <drivers/clock_control/nrf_clock_control.h>
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#include <hal/nrf_rtc.h>
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#include <sys/atomic.h>
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#ifdef DPPI_PRESENT
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#include <nrfx_dppi.h>
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#else
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#include <nrfx_ppi.h>
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#endif
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#define LOG_MODULE_NAME counter_rtc
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#include <logging/log.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_COUNTER_LOG_LEVEL);
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#define ERR(...) LOG_INST_ERR(get_nrfx_config(dev)->log, __VA_ARGS__)
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#define WRN(...) LOG_INST_WRN(get_nrfx_config(dev)->log, __VA_ARGS__)
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#define INF(...) LOG_INST_INF(get_nrfx_config(dev)->log, __VA_ARGS__)
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#define DBG(...) LOG_INST_DBG(get_nrfx_config(dev)->log, __VA_ARGS__)
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#define COUNTER_MAX_TOP_VALUE RTC_COUNTER_COUNTER_Msk
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#define COUNTER_GET_TOP_CH(dev) counter_get_num_of_channels(dev)
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#define IS_FIXED_TOP(dev) COND_CODE_1(CONFIG_COUNTER_RTC_CUSTOM_TOP_SUPPORT, \
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(get_nrfx_config(dev)->fixed_top), (true))
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#define IS_PPI_WRAP(dev) COND_CODE_1(CONFIG_COUNTER_RTC_WITH_PPI_WRAP, \
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(get_nrfx_config(dev)->use_ppi), (false))
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#define CC_ADJUSTED_OFFSET 16
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#define CC_ADJ_MASK(chan) (BIT(chan + CC_ADJUSTED_OFFSET))
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struct counter_nrfx_data {
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counter_top_callback_t top_cb;
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void *top_user_data;
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uint32_t top;
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uint32_t guard_period;
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/* Store channel interrupt pending and CC adjusted flags. */
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atomic_t ipend_adj;
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#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP
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uint8_t ppi_ch;
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#endif
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};
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struct counter_nrfx_ch_data {
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counter_alarm_callback_t callback;
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void *user_data;
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};
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struct counter_nrfx_config {
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struct counter_config_info info;
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struct counter_nrfx_ch_data *ch_data;
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NRF_RTC_Type *rtc;
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#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP
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bool use_ppi;
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#endif
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#if CONFIG_COUNTER_RTC_CUSTOM_TOP_SUPPORT
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bool fixed_top;
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#endif
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LOG_INSTANCE_PTR_DECLARE(log);
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};
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static inline struct counter_nrfx_data *get_dev_data(const struct device *dev)
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{
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return dev->data;
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}
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static inline const struct counter_nrfx_config *get_nrfx_config(const struct device *dev)
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{
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return CONTAINER_OF(dev->config,
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struct counter_nrfx_config, info);
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}
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static int start(const struct device *dev)
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{
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nrf_rtc_task_trigger(get_nrfx_config(dev)->rtc, NRF_RTC_TASK_START);
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return 0;
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}
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static int stop(const struct device *dev)
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{
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nrf_rtc_task_trigger(get_nrfx_config(dev)->rtc, NRF_RTC_TASK_STOP);
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return 0;
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}
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static uint32_t read(const struct device *dev)
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{
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return nrf_rtc_counter_get(get_nrfx_config(dev)->rtc);
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}
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static int get_value(const struct device *dev, uint32_t *ticks)
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{
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*ticks = read(dev);
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return 0;
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}
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/* Return true if value equals 2^n - 1 */
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static inline bool is_bit_mask(uint32_t val)
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{
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return !(val & (val + 1));
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}
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/* Function calculates distance between to values assuming that one first
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* argument is in front and that values wrap.
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*/
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static uint32_t ticks_sub(const struct device *dev, uint32_t val,
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uint32_t old, uint32_t top)
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{
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if (IS_FIXED_TOP(dev)) {
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return (val - old) & COUNTER_MAX_TOP_VALUE;
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} else if (likely(is_bit_mask(top))) {
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return (val - old) & top;
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}
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/* if top is not 2^n-1 */
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return (val >= old) ? (val - old) : val + top + 1 - old;
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}
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static uint32_t skip_zero_on_custom_top(uint32_t val, uint32_t top)
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{
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/* From Product Specification: If a CC register value is 0 when
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* a CLEAR task is set, this will not trigger a COMPARE event.
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*/
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if (unlikely(val == 0) && (top != COUNTER_MAX_TOP_VALUE)) {
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val++;
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}
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return val;
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}
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static uint32_t ticks_add(const struct device *dev, uint32_t val1,
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uint32_t val2, uint32_t top)
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{
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uint32_t sum = val1 + val2;
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if (IS_FIXED_TOP(dev)) {
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ARG_UNUSED(top);
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return sum & COUNTER_MAX_TOP_VALUE;
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}
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if (likely(is_bit_mask(top))) {
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sum = sum & top;
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} else {
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sum = sum > top ? sum - (top + 1) : sum;
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}
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return skip_zero_on_custom_top(sum, top);
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}
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static void set_cc_int_pending(const struct device *dev, uint8_t chan)
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{
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atomic_or(&get_dev_data(dev)->ipend_adj, BIT(chan));
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NRFX_IRQ_PENDING_SET(NRFX_IRQ_NUMBER_GET(get_nrfx_config(dev)->rtc));
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}
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/** @brief Handle case when CC value equals COUNTER+1.
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*
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* RTC will not generate event if CC value equals COUNTER+1. If such CC is
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* about to be set then special algorithm is applied. Since counter must not
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* expire before expected value, CC is set to COUNTER+2. If COUNTER progressed
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* during that time it means that target value is reached and interrupt is
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* manually triggered. If not then interrupt is enabled since it is expected
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* that CC value will generate event.
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*
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* Additionally, an information about CC adjustment is stored. This information
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* is used in the callback to return original CC value which was requested by
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* the user.
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*/
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static void handle_next_tick_case(const struct device *dev, uint8_t chan,
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uint32_t now, uint32_t val)
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{
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val = ticks_add(dev, val, 1, get_dev_data(dev)->top);
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nrf_rtc_cc_set(get_nrfx_config(dev)->rtc, chan, val);
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atomic_or(&get_dev_data(dev)->ipend_adj, CC_ADJ_MASK(chan));
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if (nrf_rtc_counter_get(get_nrfx_config(dev)->rtc) != now) {
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set_cc_int_pending(dev, chan);
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} else {
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nrf_rtc_int_enable(get_nrfx_config(dev)->rtc,
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RTC_CHANNEL_INT_MASK(chan));
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}
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}
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/*
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* @brief Set COMPARE value with optional too late setting detection.
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*
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* Setting CC algorithm takes into account:
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* - Current COMPARE value written to the register may be close to the current
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* COUNTER value thus COMPARE event may be generated at any moment
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* - Next COMPARE value may be soon in the future. Taking into account potential
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* preemption COMPARE value may be set too late.
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* - RTC registers are clocked with LF clock (32kHz) and sampled between two
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* LF ticks.
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* - Setting COMPARE register to COUNTER+1 does not generate COMPARE event if
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* done half tick before tick boundary.
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*
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* Algorithm assumes that:
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* - COMPARE interrupt is disabled
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* - absolute value is taking into account guard period. It means that
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* it won't be further in future than <top> - <guard_period> from now.
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*
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* @param dev Device.
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* @param chan COMPARE channel.
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* @param val Value (absolute or relative).
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* @param flags Alarm flags.
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*
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* @retval 0 if COMPARE value was set on time and COMPARE interrupt is expected.
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* @retval -ETIME if absolute alarm was set too late and error reporting is
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* enabled.
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*
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*/
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static int set_cc(const struct device *dev, uint8_t chan, uint32_t val,
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uint32_t flags)
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{
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__ASSERT_NO_MSG(get_dev_data(dev)->guard_period <
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get_dev_data(dev)->top);
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NRF_RTC_Type *rtc = get_nrfx_config(dev)->rtc;
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nrf_rtc_event_t evt;
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uint32_t prev_val;
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uint32_t top;
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uint32_t now;
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uint32_t diff;
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uint32_t int_mask = RTC_CHANNEL_INT_MASK(chan);
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int err = 0;
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uint32_t max_rel_val;
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bool absolute = flags & COUNTER_ALARM_CFG_ABSOLUTE;
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bool irq_on_late;
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__ASSERT(nrf_rtc_int_enable_check(rtc, int_mask) == 0,
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"Expected that CC interrupt is disabled.");
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evt = RTC_CHANNEL_EVENT_ADDR(chan);
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top = get_dev_data(dev)->top;
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now = nrf_rtc_counter_get(rtc);
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/* First take care of a risk of an event coming from CC being set to
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* next tick. Reconfigure CC to future (now tick is the furtherest
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* future). If CC was set to next tick we need to wait for up to 15us
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* (half of 32k tick) and clean potential event. After that time there
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* is no risk of unwanted event.
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*/
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prev_val = nrf_rtc_cc_get(rtc, chan);
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nrf_rtc_event_clear(rtc, evt);
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nrf_rtc_cc_set(rtc, chan, now);
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nrf_rtc_event_enable(rtc, int_mask);
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if (ticks_sub(dev, prev_val, now, top) == 1) {
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NRFX_DELAY_US(15);
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nrf_rtc_event_clear(rtc, evt);
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}
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now = nrf_rtc_counter_get(rtc);
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if (absolute) {
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val = skip_zero_on_custom_top(val, top);
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irq_on_late = flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE;
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max_rel_val = top - get_dev_data(dev)->guard_period;
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} else {
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/* If relative value is smaller than half of the counter range
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* it is assumed that there is a risk of setting value too late
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* and late detection algorithm must be applied. When late
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* setting is detected, interrupt shall be triggered for
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* immediate expiration of the timer. Detection is performed
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* by limiting relative distance between CC and counter.
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*
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* Note that half of counter range is an arbitrary value.
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*/
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irq_on_late = val < (top / 2);
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/* limit max to detect short relative being set too late. */
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max_rel_val = irq_on_late ? top / 2 : top;
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val = ticks_add(dev, now, val, top);
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}
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diff = ticks_sub(dev, val, now, top);
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if (diff == 1) {
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/* CC cannot be set to COUNTER+1 because that will not
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* generate an event. In that case, special handling is
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* performed (attempt to set CC to COUNTER+2).
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*/
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handle_next_tick_case(dev, chan, now, val);
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} else {
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nrf_rtc_cc_set(rtc, chan, val);
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now = nrf_rtc_counter_get(rtc);
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/* decrement value to detect also case when val == read(dev).
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* Otherwise, condition would need to include comparing diff
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* against 0.
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*/
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diff = ticks_sub(dev, val - 1, now, top);
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if (diff > max_rel_val) {
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if (absolute) {
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err = -ETIME;
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}
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/* Interrupt is triggered always for relative alarm and
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* for absolute depending on the flag.
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*/
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if (irq_on_late) {
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set_cc_int_pending(dev, chan);
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} else {
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get_nrfx_config(dev)->ch_data[chan].callback =
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NULL;
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}
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} else if (diff == 0) {
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/* It is possible that setting CC was interrupted and
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* CC might be set to COUNTER+1 value which will not
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* generate an event. In that case, special handling
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* is performed (attempt to set CC to COUNTER+2).
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*/
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handle_next_tick_case(dev, chan, now, val);
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} else {
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nrf_rtc_int_enable(rtc, int_mask);
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}
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}
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return err;
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}
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static int set_channel_alarm(const struct device *dev, uint8_t chan,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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const struct counter_nrfx_config *nrfx_config = get_nrfx_config(dev);
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struct counter_nrfx_ch_data *chdata = &nrfx_config->ch_data[chan];
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if (alarm_cfg->ticks > get_dev_data(dev)->top) {
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return -EINVAL;
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}
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if (chdata->callback) {
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return -EBUSY;
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}
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chdata->callback = alarm_cfg->callback;
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chdata->user_data = alarm_cfg->user_data;
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atomic_and(&get_dev_data(dev)->ipend_adj, ~CC_ADJ_MASK(chan));
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return set_cc(dev, chan, alarm_cfg->ticks, alarm_cfg->flags);
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}
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static void disable(const struct device *dev, uint8_t chan)
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{
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const struct counter_nrfx_config *config = get_nrfx_config(dev);
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NRF_RTC_Type *rtc = config->rtc;
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nrf_rtc_event_t evt = RTC_CHANNEL_EVENT_ADDR(chan);
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nrf_rtc_int_disable(rtc, RTC_CHANNEL_INT_MASK(chan));
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nrf_rtc_event_disable(rtc, RTC_CHANNEL_INT_MASK(chan));
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nrf_rtc_event_clear(rtc, evt);
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config->ch_data[chan].callback = NULL;
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}
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static int cancel_alarm(const struct device *dev, uint8_t chan_id)
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{
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disable(dev, chan_id);
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return 0;
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}
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static int ppi_setup(const struct device *dev, uint8_t chan)
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{
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#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP
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const struct counter_nrfx_config *nrfx_config = get_nrfx_config(dev);
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struct counter_nrfx_data *data = get_dev_data(dev);
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NRF_RTC_Type *rtc = nrfx_config->rtc;
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nrf_rtc_event_t evt = RTC_CHANNEL_EVENT_ADDR(chan);
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nrfx_err_t result;
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if (!nrfx_config->use_ppi) {
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return 0;
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}
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nrf_rtc_event_enable(rtc, RTC_CHANNEL_INT_MASK(chan));
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#ifdef DPPI_PRESENT
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result = nrfx_dppi_channel_alloc(&data->ppi_ch);
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if (result != NRFX_SUCCESS) {
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ERR("Failed to allocate PPI channel.");
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return -ENODEV;
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}
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nrf_rtc_subscribe_set(rtc, NRF_RTC_TASK_CLEAR, data->ppi_ch);
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nrf_rtc_publish_set(rtc->p_reg, evt, data->ppi_ch);
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(void)nrfx_dppi_channel_enable(data->ppi_ch);
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#else /* DPPI_PRESENT */
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uint32_t evt_addr;
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uint32_t task_addr;
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evt_addr = nrf_rtc_event_address_get(rtc, evt);
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task_addr = nrf_rtc_task_address_get(rtc, NRF_RTC_TASK_CLEAR);
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result = nrfx_ppi_channel_alloc(&data->ppi_ch);
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if (result != NRFX_SUCCESS) {
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ERR("Failed to allocate PPI channel.");
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return -ENODEV;
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}
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(void)nrfx_ppi_channel_assign(data->ppi_ch, evt_addr, task_addr);
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(void)nrfx_ppi_channel_enable(data->ppi_ch);
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#endif
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#endif /* CONFIG_COUNTER_RTC_WITH_PPI_WRAP */
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return 0;
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}
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static void ppi_free(const struct device *dev, uint8_t chan)
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{
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#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP
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const struct counter_nrfx_config *nrfx_config = get_nrfx_config(dev);
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uint8_t ppi_ch = get_dev_data(dev)->ppi_ch;
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NRF_RTC_Type *rtc = nrfx_config->rtc;
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if (!nrfx_config->use_ppi) {
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return;
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}
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nrf_rtc_event_disable(rtc, RTC_CHANNEL_INT_MASK(chan));
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#ifdef DPPI_PRESENT
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NRF_RTC_Type *rtc = nrfx_config->rtc;
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nrf_rtc_event_t evt = RTC_CHANNEL_EVENT_ADDR(chan);
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(void)nrfx_dppi_channel_disable(ppi_ch);
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nrf_rtc_subscribe_clear(rtc, NRF_RTC_TASK_CLEAR);
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nrf_rtc_publish_clear(rtc, evt);
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(void)nrfx_dppi_channel_free(ppi_ch);
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#else /* DPPI_PRESENT */
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(void)nrfx_ppi_channel_disable(ppi_ch);
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(void)nrfx_ppi_channel_free(ppi_ch);
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#endif
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#endif
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}
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/* Return true if counter must be cleared by the CPU. It is cleared
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* automatically in case of max top value or PPI usage.
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*/
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static bool sw_wrap_required(const struct device *dev)
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{
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return (get_dev_data(dev)->top != COUNTER_MAX_TOP_VALUE)
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&& !IS_PPI_WRAP(dev);
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}
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static int set_fixed_top_value(const struct device *dev,
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const struct counter_top_cfg *cfg)
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{
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NRF_RTC_Type *rtc = get_nrfx_config(dev)->rtc;
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if (cfg->ticks != COUNTER_MAX_TOP_VALUE) {
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return -EINVAL;
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}
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nrf_rtc_int_disable(rtc, NRF_RTC_INT_OVERFLOW_MASK);
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get_dev_data(dev)->top_cb = cfg->callback;
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get_dev_data(dev)->top_user_data = cfg->user_data;
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if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
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nrf_rtc_task_trigger(rtc, NRF_RTC_TASK_CLEAR);
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}
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if (cfg->callback) {
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nrf_rtc_int_enable(rtc, NRF_RTC_INT_OVERFLOW_MASK);
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}
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return 0;
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}
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static int set_top_value(const struct device *dev,
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const struct counter_top_cfg *cfg)
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{
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const struct counter_nrfx_config *nrfx_config = get_nrfx_config(dev);
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NRF_RTC_Type *rtc = nrfx_config->rtc;
|
|
struct counter_nrfx_data *dev_data = get_dev_data(dev);
|
|
uint32_t top_ch = COUNTER_GET_TOP_CH(dev);
|
|
int err = 0;
|
|
|
|
if (IS_FIXED_TOP(dev)) {
|
|
return set_fixed_top_value(dev, cfg);
|
|
}
|
|
|
|
for (int i = 0; i < counter_get_num_of_channels(dev); i++) {
|
|
/* Overflow can be changed only when all alarms are
|
|
* disables.
|
|
*/
|
|
if (nrfx_config->ch_data[i].callback) {
|
|
return -EBUSY;
|
|
}
|
|
}
|
|
|
|
nrf_rtc_int_disable(rtc, RTC_CHANNEL_INT_MASK(top_ch));
|
|
|
|
if (IS_PPI_WRAP(dev)) {
|
|
if ((dev_data->top == COUNTER_MAX_TOP_VALUE) &&
|
|
cfg->ticks != COUNTER_MAX_TOP_VALUE) {
|
|
err = ppi_setup(dev, top_ch);
|
|
} else if (((dev_data->top != COUNTER_MAX_TOP_VALUE) &&
|
|
cfg->ticks == COUNTER_MAX_TOP_VALUE)) {
|
|
ppi_free(dev, top_ch);
|
|
}
|
|
}
|
|
|
|
dev_data->top_cb = cfg->callback;
|
|
dev_data->top_user_data = cfg->user_data;
|
|
dev_data->top = cfg->ticks;
|
|
nrf_rtc_cc_set(rtc, top_ch, cfg->ticks);
|
|
|
|
if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
|
|
nrf_rtc_task_trigger(rtc, NRF_RTC_TASK_CLEAR);
|
|
} else if (read(dev) >= cfg->ticks) {
|
|
err = -ETIME;
|
|
if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
|
|
nrf_rtc_task_trigger(rtc, NRF_RTC_TASK_CLEAR);
|
|
}
|
|
}
|
|
|
|
if (cfg->callback || sw_wrap_required(dev)) {
|
|
nrf_rtc_int_enable(rtc, RTC_CHANNEL_INT_MASK(top_ch));
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static uint32_t get_pending_int(const struct device *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int init_rtc(const struct device *dev, uint32_t prescaler)
|
|
{
|
|
const struct counter_nrfx_config *nrfx_config = get_nrfx_config(dev);
|
|
struct counter_top_cfg top_cfg = {
|
|
.ticks = COUNTER_MAX_TOP_VALUE
|
|
};
|
|
NRF_RTC_Type *rtc = nrfx_config->rtc;
|
|
int err;
|
|
|
|
z_nrf_clock_control_lf_on(CLOCK_CONTROL_NRF_LF_START_NOWAIT);
|
|
|
|
nrf_rtc_prescaler_set(rtc, prescaler);
|
|
|
|
NRFX_IRQ_ENABLE(NRFX_IRQ_NUMBER_GET(rtc));
|
|
|
|
get_dev_data(dev)->top = COUNTER_MAX_TOP_VALUE;
|
|
err = set_top_value(dev, &top_cfg);
|
|
DBG("Initialized");
|
|
|
|
return err;
|
|
}
|
|
|
|
static uint32_t get_top_value(const struct device *dev)
|
|
{
|
|
return get_dev_data(dev)->top;
|
|
}
|
|
|
|
static uint32_t get_guard_period(const struct device *dev, uint32_t flags)
|
|
{
|
|
return get_dev_data(dev)->guard_period;
|
|
}
|
|
|
|
static int set_guard_period(const struct device *dev, uint32_t guard,
|
|
uint32_t flags)
|
|
{
|
|
get_dev_data(dev)->guard_period = guard;
|
|
return 0;
|
|
}
|
|
|
|
static void top_irq_handle(const struct device *dev)
|
|
{
|
|
NRF_RTC_Type *rtc = get_nrfx_config(dev)->rtc;
|
|
counter_top_callback_t cb = get_dev_data(dev)->top_cb;
|
|
nrf_rtc_event_t top_evt;
|
|
|
|
top_evt = IS_FIXED_TOP(dev) ?
|
|
NRF_RTC_EVENT_OVERFLOW :
|
|
RTC_CHANNEL_EVENT_ADDR(counter_get_num_of_channels(dev));
|
|
|
|
if (nrf_rtc_event_check(rtc, top_evt)) {
|
|
nrf_rtc_event_clear(rtc, top_evt);
|
|
|
|
/* Perform manual clear if custom top value is used and PPI
|
|
* clearing is not used.
|
|
*/
|
|
if (!IS_FIXED_TOP(dev) && !IS_PPI_WRAP(dev)) {
|
|
nrf_rtc_task_trigger(rtc, NRF_RTC_TASK_CLEAR);
|
|
}
|
|
|
|
if (cb) {
|
|
cb(dev, get_dev_data(dev)->top_user_data);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void alarm_irq_handle(const struct device *dev, uint32_t chan)
|
|
{
|
|
NRF_RTC_Type *rtc = get_nrfx_config(dev)->rtc;
|
|
nrf_rtc_event_t evt = RTC_CHANNEL_EVENT_ADDR(chan);
|
|
uint32_t int_mask = RTC_CHANNEL_INT_MASK(chan);
|
|
bool hw_irq_pending = nrf_rtc_event_check(rtc, evt) &&
|
|
nrf_rtc_int_enable_check(rtc, int_mask);
|
|
bool sw_irq_pending = get_dev_data(dev)->ipend_adj & BIT(chan);
|
|
|
|
if (hw_irq_pending || sw_irq_pending) {
|
|
struct counter_nrfx_ch_data *chdata;
|
|
counter_alarm_callback_t cb;
|
|
|
|
nrf_rtc_event_clear(rtc, evt);
|
|
atomic_and(&get_dev_data(dev)->ipend_adj, ~BIT(chan));
|
|
nrf_rtc_int_disable(rtc, int_mask);
|
|
|
|
chdata = &get_nrfx_config(dev)->ch_data[chan];
|
|
cb = chdata->callback;
|
|
chdata->callback = NULL;
|
|
|
|
if (cb) {
|
|
uint32_t cc = nrf_rtc_cc_get(rtc, chan);
|
|
|
|
if (get_dev_data(dev)->ipend_adj & CC_ADJ_MASK(chan)) {
|
|
cc = ticks_sub(dev, cc, 1,
|
|
get_dev_data(dev)->top);
|
|
}
|
|
|
|
cb(dev, chan, cc, chdata->user_data);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void irq_handler(const struct device *dev)
|
|
{
|
|
top_irq_handle(dev);
|
|
|
|
for (uint32_t i = 0; i < counter_get_num_of_channels(dev); i++) {
|
|
alarm_irq_handle(dev, i);
|
|
}
|
|
}
|
|
|
|
static const struct counter_driver_api counter_nrfx_driver_api = {
|
|
.start = start,
|
|
.stop = stop,
|
|
.get_value = get_value,
|
|
.set_alarm = set_channel_alarm,
|
|
.cancel_alarm = cancel_alarm,
|
|
.set_top_value = set_top_value,
|
|
.get_pending_int = get_pending_int,
|
|
.get_top_value = get_top_value,
|
|
.get_guard_period = get_guard_period,
|
|
.set_guard_period = set_guard_period,
|
|
};
|
|
|
|
/*
|
|
* Devicetree access is done with node labels due to HAL API
|
|
* requirements. In particular, RTCx_CC_NUM values from HALs
|
|
* are indexed by peripheral number, so DT_INST APIs won't work.
|
|
*/
|
|
|
|
#define RTC(idx) DT_NODELABEL(rtc##idx)
|
|
#define RTC_PROP(idx, prop) DT_PROP(RTC(idx), prop)
|
|
|
|
#define COUNTER_NRF_RTC_DEVICE(idx) \
|
|
BUILD_ASSERT((RTC_PROP(idx, prescaler) - 1) <= \
|
|
RTC_PRESCALER_PRESCALER_Msk, \
|
|
"RTC prescaler out of range"); \
|
|
static int counter_##idx##_init(const struct device *dev) \
|
|
{ \
|
|
IRQ_CONNECT(DT_IRQN(RTC(idx)), DT_IRQ(RTC(idx), priority), \
|
|
irq_handler, DEVICE_DT_GET(RTC(idx)), 0); \
|
|
return init_rtc(dev, RTC_PROP(idx, prescaler) - 1); \
|
|
} \
|
|
static struct counter_nrfx_data counter_##idx##_data; \
|
|
static struct counter_nrfx_ch_data \
|
|
counter##idx##_ch_data[RTC##idx##_CC_NUM]; \
|
|
LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_COUNTER_LOG_LEVEL); \
|
|
static const struct counter_nrfx_config nrfx_counter_##idx##_config = {\
|
|
.info = { \
|
|
.max_top_value = COUNTER_MAX_TOP_VALUE, \
|
|
.freq = RTC_PROP(idx, clock_frequency) / \
|
|
RTC_PROP(idx, prescaler), \
|
|
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
|
|
.channels = RTC_PROP(idx, fixed_top) ? \
|
|
RTC##idx##_CC_NUM : RTC##idx##_CC_NUM - 1 \
|
|
}, \
|
|
.ch_data = counter##idx##_ch_data, \
|
|
.rtc = (NRF_RTC_Type *)DT_REG_ADDR(RTC(idx)), \
|
|
IF_ENABLED(CONFIG_COUNTER_RTC_WITH_PPI_WRAP, \
|
|
(.use_ppi = RTC_PROP(idx, ppi_wrap),)) \
|
|
IF_ENABLED(CONFIG_COUNTER_RTC_CUSTOM_TOP_SUPPORT, \
|
|
(.fixed_top = RTC_PROP(idx, fixed_top),)) \
|
|
LOG_INSTANCE_PTR_INIT(log, LOG_MODULE_NAME, idx) \
|
|
}; \
|
|
DEVICE_DT_DEFINE(RTC(idx), \
|
|
counter_##idx##_init, \
|
|
NULL, \
|
|
&counter_##idx##_data, \
|
|
&nrfx_counter_##idx##_config.info, \
|
|
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
|
&counter_nrfx_driver_api)
|
|
|
|
#ifdef CONFIG_COUNTER_RTC0
|
|
COUNTER_NRF_RTC_DEVICE(0);
|
|
#endif
|
|
|
|
#ifdef CONFIG_COUNTER_RTC1
|
|
COUNTER_NRF_RTC_DEVICE(1);
|
|
#endif
|
|
|
|
#ifdef CONFIG_COUNTER_RTC2
|
|
COUNTER_NRF_RTC_DEVICE(2);
|
|
#endif
|