zephyr/soc/xtensa/intel_adsp
Kai Vehmanen a8af622f68 soc: xtensa: intel_adsp: restore bootctl with per-core state
When exiting PM_STATE_SOFT_OFF, the primary core state is always
used to restore bootctl register and the clock and power gating
settings.

This can lead to problems if non-primary core is powered up and down
many times before primary core 0 is powered down the first time.
The saved state in core_desc[0].bctl will be null, and as a result-
power gating and clock gating is not disabled correctly for
non-primary cores.

Link: https://github.com/thesofproject/sof/issues/8642
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-02-13 11:13:05 +01:00
..
ace soc: xtensa: intel_adsp: restore bootctl with per-core state 2024-02-13 11:13:05 +01:00
cavs xtensa: move to use system cache API support for coherency 2024-02-03 13:42:33 -05:00
common xtensa: move to use system cache API support for coherency 2024-02-03 13:42:33 -05:00
tools
CMakeLists.txt
Kconfig xtensa: move to use system cache API support for coherency 2024-02-03 13:42:33 -05:00
Kconfig.defconfig
Kconfig.soc