105 lines
3.2 KiB
YAML
105 lines
3.2 KiB
YAML
# Copyright (c) 2021, STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 OSPI Flash controller supporting the JEDEC CFI interface
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Representation of a serial flash on a octospi bus:
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mx25lm51245: ospi-nor-flash@70000000 {
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compatible = "st,stm32-ospi-nor";
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reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits */
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data-mode = <OSPI_OPI_MODE>; /* access on 8 data lines */
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data-rate = <OSPI_DTR_TRANSFER>; /* access in DTR */
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ospi-max-frequency = <DT_FREQ_M(50)>;
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status = "okay";
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};
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compatible: "st,stm32-ospi-nor"
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include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
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on-bus: ospi
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properties:
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reg:
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required: true
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description: Flash Memory base address and size in bytes
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ospi-max-frequency:
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type: int
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required: true
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description: Maximum clock frequency of device's OSPI interface in Hz
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reset-gpios:
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type: phandle-array
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description: RESETn pin
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spi-bus-width:
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type: int
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required: true
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description: |
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The width of (Octo)SPI bus to which flash memory is connected.
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Possible values are :
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- OSPI_SPI_MODE <1> = SPI mode on 1 data line
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- OSPI_DUAL_MODE <2> = Dual mode on 2 data lines
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- OSPI_QUAD_MODE <4> = Quad mode on 4 data lines
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- OSPI_OPI_MODE <8> = Octo mode on 8 data lines
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enum:
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- 1
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- 2
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- 4
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- 8
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data-rate:
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type: int
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required: true
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description: |
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The SPI data Rate is STR or DTR
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Possible values are :
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- OSPI_STR_TRANSFER <1> = Single Rate Transfer
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- OSPI_DTR_TRANSFER <2> = Dual Rate Transfer (only with OSPI_OPI_MODE)
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enum:
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- 1
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- 2
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writeoc:
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type: string
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enum:
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- "PP" # Page program, PP (0x02) up to 256 bytes
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- "PP_1_1_2" # Dual page program, PP 1-1-2 (0xA2)
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- "PP_1_1_4" # Quad data line SPI, PP 1-1-4 (0x32)
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- "PP_1_4_4" # Quad data line SPI, PP 1-4-4 (0x38)
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description: |
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The value encodes number of I/O lines used for the opcode,
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address, and data.
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There is no info about quad page program opcodes in the SFDP
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tables, hence it has been assumed that NOR flash memory
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supporting 1-4-4 mode also would support fast page programming.
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Intended for modes other than OSPI_OPI_MODE.
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If absent, then program page opcode is determined by the
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`spi-bus-width`:
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* OSPI_SPI_MODE -> PP 1-1-1 (0x02)
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* OSPI_DUAL_MODE -> PP 1-1-2 (0xA2)
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* OSPI_QUAD_MODE -> PP 1-4-4 (0x38)
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four-byte-opcodes:
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type: boolean
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description: |
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Some NOR-Flash ICs use different opcodes when operating in
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4 byte addressing mode.
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When enabled, then 3 byte opcodes will be converted to
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4 byte opcodes.
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* PP 1-1-1 (0x02) -> PP 1-1-1 4B (0x12)
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* PP 1-1-4 (0x32) -> PP 1-1-4 4B (0x34)
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* PP 1-4-4 (0x38) -> PP 1-4-4 4B (0x3E)
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* READ 1-1-1 (0x03) -> READ 1-1-1 4B (0x13)
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* READ FAST 1-1-1 (0x0B) -> READ FAST 1-1-1 4B (0x0C)
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* DREAD 1-1-2 (0x3B) -> DREAD 1-1-2 4B (0x3C)
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* 2READ 1-2-2 (0xBB) -> 2READ 1-2-2 4B (0xBC)
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* QREAD 1-1-4 (0x6B) -> QREAD 1-1-4 4B (0x6C)
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* 4READ 1-4-4 (0xEB) -> 4READ 1-4-4 4B (0xEC)
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