484 lines
12 KiB
C
484 lines
12 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief PCI probe and information routines
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*
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* Module implements routines for PCI bus initialization and query.
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*
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* USAGE
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* To use the driver, the platform must define:
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* - Numbers of BUSes:
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* - PCI_BUS_NUMBERS;
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* - Register addresses:
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* - PCI_CTRL_ADDR_REG;
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* - PCI_CTRL_DATA_REG;
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* - pci_pin2irq() - the routine that converts the PCI interrupt pin
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* number to IRQ number.
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*
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* About scanning the PCI buses:
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* At every new usage of this API, the code should call pci_bus_scan_init().
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* It should own a struct pci_dev_info, filled in with the parameters it is
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* interested to look for: class and/or vendor_id/device_id.
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*
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* Then it can loop on pci_bus_scan() providing a pointer on that structure.
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* Such function can be called as long as it returns 1. At every successful
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* return of pci_bus_scan() it means the provided structure pointer will have
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* been updated with the current scan result which the code might be interested
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* in. On pci_bus_scan() returning 0, the code should discard the result and
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* stop calling pci_bus_scan(). If it wants to retrieve the result, it will
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* have to restart the procedure all over again.
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*
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* EXAMPLE
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* struct pci_dev_info info = {
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* .class_type = PCI_CLASS_COMM_CTLR
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* };
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*
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* pci_bus_scan_init();
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*
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* while (pci_bus_scan(&info) {
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* // do something with "info" which holds a valid result, i.e. some
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* // device information matching the PCI class PCI_CLASS_COMM_CTLR
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* }
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*
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* INTERNALS
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* The whole logic runs around a structure: struct lookup_data, which exists
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* on one instanciation called 'lookup'.
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* Such structure is used for 2 distinct roles:
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* - to match devices the caller is looking for
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* - to loop on PCI bus, devices, function and BARs
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*
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* The search criterias are the class and/or the vendor_id/device_id of a PCI
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* device. The caller first initializes the lookup structure by calling
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* pci_bus_scan_init(), which will reset the search criterias as well as the
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* loop paramaters to 0. At the very first subsequent call of pci_bus_scan()
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* the lookup structure will store the search criterias. Then the loop starts.
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* For each bus it will run through each device on which it will loop on each
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* function and BARs, as long as the criterias does not match or until it hit
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* the limit of bus/dev/functions to scan.
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*
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* On a successful match, it will stop the loop, fill in the caller's
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* pci_dev_info structure with the found device information, and return 1.
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* Hopefully, the lookup structure still remembers where it stopped and the
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* original search criterias. Thus, when the caller asks to scan again for
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* a possible result next, the loop will restart where it stopped.
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* That will work as long as there are relevant results found.
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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#include <misc/printk.h>
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#include <toolchain.h>
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#include <sections.h>
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#include <board.h>
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#include <pci/pci_mgr.h>
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#include <pci/pci.h>
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#ifdef CONFIG_PCI_ENUMERATION
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/* NOTE. These parameters may need to be configurable */
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#define LSPCI_MAX_BUS PCI_BUS_NUMBERS /* maximum number of buses to scan */
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#define LSPCI_MAX_DEV 32 /* maximum number of devices to scan */
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#define LSPCI_MAX_FUNC PCI_MAX_FUNCTIONS /* maximum functions to scan */
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#define LSPCI_MAX_REG 64 /* maximum device registers to read */
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/* Base Address Register configuration fields */
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#define BAR_SPACE(x) ((x) & 0x00000001)
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#define BAR_TYPE(x) ((x) & 0x00000006)
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#define BAR_TYPE_32BIT 0
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#define BAR_TYPE_64BIT 4
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#define BAR_PREFETCH(x) (((x) >> 3) & 0x00000001)
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#define BAR_ADDR(x) (((x) >> 4) & 0x0fffffff)
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#define BAR_IO_MASK(x) ((x) & ~0x3)
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#define BAR_MEM_MASK(x) ((x) & ~0xf)
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struct lookup_data {
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struct pci_dev_info info;
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uint32_t bus:9;
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uint32_t dev:6;
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uint32_t func:4;
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uint32_t baridx:3;
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uint32_t barofs:3;
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uint32_t unused:7;
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};
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static struct lookup_data __noinit lookup;
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/**
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*
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* @brief Return the configuration for the specified BAR
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*
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* @return 0 if BAR is implemented, -1 if not.
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*/
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static inline int pci_bar_config_get(union pci_addr_reg pci_ctrl_addr,
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uint32_t *config)
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{
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uint32_t old_value;
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/* save the current setting */
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(old_value),
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&old_value);
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/* write to the BAR to see how large it is */
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pci_write(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(uint32_t),
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0xffffffff);
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(*config),
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config);
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/* put back the old configuration */
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pci_write(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(old_value),
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old_value);
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/* check if this BAR is implemented */
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if (*config != 0xffffffff && *config != 0) {
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return 0;
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}
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/* BAR not supported */
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return -1;
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}
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/**
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*
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* @brief Retrieve the I/O address and IRQ of the specified BAR
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*
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* @return -1 on error, 0 if 32 bit BAR retrieved or 1 if 64 bit BAR retrieved
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*
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* NOTE: Routine does not set up parameters for 64 bit BARS, they are ignored.
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*/
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static inline int pci_bar_params_get(union pci_addr_reg pci_ctrl_addr,
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struct pci_dev_info *dev_info,
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int max_bars)
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{
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uint32_t bar_value;
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uint32_t bar_config;
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uint32_t bar_hival;
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uint32_t addr;
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uint32_t mask;
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pci_ctrl_addr.field.reg = 4 + lookup.barofs;
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(bar_value),
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&bar_value);
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if (pci_bar_config_get(pci_ctrl_addr, &bar_config) != 0) {
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return -1;
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}
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if (BAR_SPACE(bar_config) == BAR_SPACE_MEM) {
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dev_info->mem_type = BAR_SPACE_MEM;
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mask = ~0xf;
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if (BAR_TYPE(bar_config) == BAR_TYPE_64BIT) {
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/* Last BAR register cannot be 64-bit */
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if (++lookup.barofs >= max_bars)
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return 1;
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/* Make sure the address is accessible */
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pci_ctrl_addr.field.reg++;
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(bar_hival),
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&bar_hival);
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if (bar_hival)
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return 1; /* Inaccessible memory */
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}
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} else {
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dev_info->mem_type = BAR_SPACE_IO;
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mask = ~0x3;
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}
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dev_info->addr = bar_value & mask;
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addr = bar_config & mask;
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if (addr != 0) {
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/* calculate the size of the BAR memory required */
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dev_info->size = 1 << (find_lsb_set(addr) - 1);
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}
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return 0;
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}
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/**
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*
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* @brief Scan the specified PCI device for all sub functions
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*
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* @return 1 if a device has been found, 0 otherwise.
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*/
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static inline int pci_dev_scan(union pci_addr_reg pci_ctrl_addr,
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struct pci_dev_info *dev_info)
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{
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static union pci_dev pci_dev_header;
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uint32_t pci_data;
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int max_bars;
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/* verify first if there is a valid device at this point */
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pci_ctrl_addr.field.func = 0;
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(pci_data),
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&pci_data);
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if (pci_data == 0xffffffff) {
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return 0;
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}
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/* scan all the possible functions for this device */
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for (; lookup.func < LSPCI_MAX_FUNC;
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lookup.baridx = 0, lookup.barofs = 0, lookup.func++) {
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if (lookup.info.function != PCI_FUNCTION_ANY &&
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lookup.func != lookup.info.function) {
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return 0;
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}
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pci_ctrl_addr.field.func = lookup.func;
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if (lookup.func != 0) {
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(pci_data),
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&pci_data);
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if (pci_data == 0xffffffff) {
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continue;
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}
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}
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/* get the PCI header from the device */
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pci_header_get(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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&pci_dev_header);
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/*
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* Skip a device if its class is specified by the
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* caller and does not match
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*/
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if (lookup.info.class_type &&
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pci_dev_header.field.class != lookup.info.class_type) {
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continue;
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}
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if (lookup.info.vendor_id && lookup.info.device_id &&
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(lookup.info.vendor_id != pci_dev_header.field.vendor_id ||
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lookup.info.device_id != pci_dev_header.field.device_id)) {
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continue;
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}
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/* Get memory and interrupt information */
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if ((pci_dev_header.field.hdr_type & 0x7f) == 1) {
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max_bars = 2;
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} else {
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max_bars = PCI_MAX_BARS;
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}
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for (; lookup.barofs < max_bars;
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lookup.baridx++, lookup.barofs++) {
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/* Ignore BARs with errors */
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if (pci_bar_params_get(pci_ctrl_addr, dev_info,
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max_bars) != 0) {
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continue;
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} else if (lookup.info.bar != PCI_BAR_ANY &&
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lookup.baridx != lookup.info.bar) {
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continue;
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} else {
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dev_info->vendor_id =
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pci_dev_header.field.vendor_id;
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dev_info->device_id =
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pci_dev_header.field.device_id;
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dev_info->class_type =
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pci_dev_header.field.class;
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dev_info->irq = pci_pin2irq(
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pci_dev_header.field.interrupt_pin);
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dev_info->function = lookup.func;
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dev_info->bar = lookup.baridx;
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lookup.baridx++;
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lookup.barofs++;
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if (lookup.barofs >= max_bars) {
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lookup.baridx = 0;
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lookup.barofs = 0;
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}
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return 1;
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}
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}
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}
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return 0;
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}
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void pci_bus_scan_init(void)
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{
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lookup.info.class_type = 0;
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lookup.info.vendor_id = 0;
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lookup.info.device_id = 0;
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lookup.info.function = PCI_FUNCTION_ANY;
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lookup.info.bar = PCI_BAR_ANY;
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lookup.bus = 0;
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lookup.dev = 0;
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lookup.func = 0;
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lookup.baridx = 0;
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lookup.barofs = 0;
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}
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/**
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*
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* @brief Scans PCI bus for devices
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*
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* The routine scans the PCI bus for the devices on criterias provided in the
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* given dev_info at first call. Which criterias can be class and/or
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* vendor_id/device_id.
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*
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* @return 1 on success, 0 otherwise. On success, dev_info is filled in with
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* currently found device information
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*/
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int pci_bus_scan(struct pci_dev_info *dev_info)
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{
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union pci_addr_reg pci_ctrl_addr;
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if (!lookup.info.class_type &&
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!lookup.info.vendor_id &&
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!lookup.info.device_id &&
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lookup.info.bar == PCI_BAR_ANY &&
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lookup.info.function == PCI_FUNCTION_ANY) {
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lookup.info.class_type = dev_info->class_type;
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lookup.info.vendor_id = dev_info->vendor_id;
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lookup.info.device_id = dev_info->device_id;
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lookup.info.function = dev_info->function;
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lookup.info.bar = dev_info->bar;
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}
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/* initialise the PCI controller address register value */
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pci_ctrl_addr.value = 0;
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if (lookup.info.function != PCI_FUNCTION_ANY) {
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lookup.func = lookup.info.function;
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}
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/* run through the buses and devices */
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for (; lookup.bus < LSPCI_MAX_BUS; lookup.bus++) {
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for (; (lookup.dev < LSPCI_MAX_DEV); lookup.dev++) {
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pci_ctrl_addr.field.bus = lookup.bus;
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pci_ctrl_addr.field.device = lookup.dev;
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if (pci_dev_scan(pci_ctrl_addr, dev_info)) {
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dev_info->bus = lookup.bus;
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dev_info->dev = lookup.dev;
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return 1;
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}
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if (lookup.info.function != PCI_FUNCTION_ANY) {
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lookup.func = lookup.info.function;
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} else {
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lookup.func = 0;
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}
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}
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lookup.dev = 0;
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}
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return 0;
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}
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#endif /* CONFIG_PCI_ENUMERATION */
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static void pci_set_command_bits(struct pci_dev_info *dev_info, uint32_t bits)
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{
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union pci_addr_reg pci_ctrl_addr;
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uint32_t pci_data;
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pci_ctrl_addr.value = 0;
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pci_ctrl_addr.field.func = dev_info->function;
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pci_ctrl_addr.field.bus = dev_info->bus;
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pci_ctrl_addr.field.device = dev_info->dev;
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pci_ctrl_addr.field.reg = 1;
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#ifdef CONFIG_PCI_DEBUG
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printk("pci_set_command_bits 0x%x\n", pci_ctrl_addr);
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#endif
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(uint16_t),
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&pci_data);
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pci_data = pci_data | bits;
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pci_write(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(uint16_t),
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pci_data);
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}
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void pci_enable_regs(struct pci_dev_info *dev_info)
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{
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pci_set_command_bits(dev_info, PCI_CMD_MEM_ENABLE);
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}
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void pci_enable_bus_master(struct pci_dev_info *dev_info)
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{
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pci_set_command_bits(dev_info, PCI_CMD_MASTER_ENABLE);
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}
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#ifdef CONFIG_PCI_DEBUG
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/**
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*
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* @brief Show PCI device
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*
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* Shows the PCI device found provided as parameter.
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*
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* @return N/A
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*/
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void pci_show(struct pci_dev_info *dev_info)
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{
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printk("PCI device:\n");
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printk("%u:%u %X:%X class: 0x%X, %u, %u, %s,"
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"addrs: 0x%X-0x%X, IRQ %d\n",
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dev_info->bus,
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dev_info->dev,
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dev_info->vendor_id,
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dev_info->device_id,
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dev_info->class_type,
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dev_info->function,
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dev_info->bar,
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(dev_info->mem_type == BAR_SPACE_MEM) ? "MEM" : "I/O",
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(uint32_t)dev_info->addr,
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(uint32_t)(dev_info->addr + dev_info->size - 1),
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dev_info->irq);
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}
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#endif /* CONFIG_PCI_DEBUG */
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