85 lines
2.0 KiB
Plaintext
85 lines
2.0 KiB
Plaintext
/*
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* Copyright (c) 2017 Florian Vaussard, HEIG-VD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/f4/stm32f412.dtsi>
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/ {
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soc {
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compatible = "st,stm32f413", "st,stm32f4", "simple-bus";
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uart4: serial@40004c00 {
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compatible ="st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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resets = <&rctl STM32_RESET(APB1, 19U)>;
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interrupts = <52 0>;
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status = "disabled";
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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resets = <&rctl STM32_RESET(APB1, 20U)>;
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interrupts = <53 0>;
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status = "disabled";
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};
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uart7: serial@40007800 {
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compatible = "st,stm32-uart";
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reg = <0x40007800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
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resets = <&rctl STM32_RESET(APB1, 30U)>;
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interrupts = <82 0>;
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status = "disabled";
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};
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uart8: serial@40007c00 {
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compatible = "st,stm32-uart";
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reg = <0x40007c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
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resets = <&rctl STM32_RESET(APB1, 31U)>;
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interrupts = <83 0>;
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status = "disabled";
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};
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uart9: serial@40011800 {
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compatible = "st,stm32-uart";
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reg = <0x40011800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
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resets = <&rctl STM32_RESET(APB2, 6U)>;
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interrupts = <88 0>;
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status = "disabled";
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};
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uart10: serial@40011c00 {
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compatible = "st,stm32-uart";
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reg = <0x40011c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
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resets = <&rctl STM32_RESET(APB2, 7U)>;
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interrupts = <89 0>;
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status = "disabled";
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};
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dac1: dac@40007400 {
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compatible = "st,stm32-dac";
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reg = <0x40007400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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can3: can@40006c00 {
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compatible = "st,stm32-bxcan";
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reg = <0x40006c00 0x400>;
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interrupts = <74 0>, <75 0>, <76 0>, <77 0>;
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interrupt-names = "TX", "RX0", "RX1", "SCE";
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x08000000>;
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status = "disabled";
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};
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};
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};
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