zephyr/soc/riscv
Martin Åberg 152d3e46ad soc/riscv: add the QEMU "RISC-V VirtIO board"
The QEMU RISC-V VirtIO board is capable:
- 8 x CPU
- 256 MiB RAM
- PMP
- PCI
- ISA string: RVnnIMAFDCSU
  - mul/div
  - FPU with double precision
  - MMU
  - Compressed instructions

Devicetree was extracted from QEMU as described in virt.dtsi.
The same .dtsi SOC description is used for 32-bit and 64-bit.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-01-15 13:06:33 -05:00
..
litex-vexriscv soc: riscv: litex-vexriscv: change CSR accessors 2020-10-02 11:36:16 +02:00
openisa_rv32m1 riscv: add support for thread local storage 2020-10-24 10:52:00 -07:00
riscv-ite drivers/i2c: add i2c driver on it8xxx2 platform 2021-01-15 11:22:57 -05:00
riscv-privilege soc/riscv: add the QEMU "RISC-V VirtIO board" 2021-01-15 13:06:33 -05:00
CMakeLists.txt