102 lines
2.9 KiB
C
102 lines
2.9 KiB
C
/*
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* Copyright 2020 Broadcom
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef DMA_IPROC_PAX_V2
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#define DMA_IPROC_PAX_V2
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#include "dma_iproc_pax.h"
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#define RING_COMPLETION_INTERRUPT_STAT_MASK 0x088
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#define RING_COMPLETION_INTERRUPT_STAT_CLEAR 0x08c
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#define RING_COMPLETION_INTERRUPT_STAT 0x090
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#define RING_DISABLE_MSI_TIMEOUT 0x0a4
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/* Register RM_COMM_CONTROL fields */
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#define RM_COMM_CONTROL_MODE_MASK 0x3
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#define RM_COMM_CONTROL_MODE_SHIFT 0
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#define RM_COMM_CONTROL_MODE_DOORBELL 0x0
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#define RM_COMM_CONTROL_MODE_TOGGLE 0x2
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#define RM_COMM_CONTROL_MODE_ALL_BD_TOGGLE 0x3
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#define RM_COMM_CONTROL_CONFIG_DONE BIT(2)
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#define RM_COMM_CONTROL_LINE_INTR_EN BIT(4)
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#define RM_COMM_CONTROL_AE_TIMEOUT_EN BIT(5)
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#define RING_DISABLE_MSI_TIMEOUT_VALUE 1
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#define PAX_DMA_TYPE_SRC_DESC 0x2
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#define PAX_DMA_TYPE_DST_DESC 0x3
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#define PAX_DMA_TYPE_MEGA_SRC_DESC 0x6
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#define PAX_DMA_TYPE_MEGA_DST_DESC 0x7
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#define PAX_DMA_TYPE_PCIE_DESC 0xB
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#define PAX_DMA_NUM_BD_BUFFS 7
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/* PCIE DESC, either DST or SRC DESC */
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#define PAX_DMA_RM_DESC_BDCOUNT 2
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/* ascii signature 'V' 'P' */
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#define PAX_DMA_WRITE_SYNC_SIGNATURE 0x5650
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#define PAX_DMA_PCI_ADDR_MSB8_SHIFT 56
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#define PAX_DMA_PCI_ADDR_HI_MSB8(pci) ((pci) >> PAX_DMA_PCI_ADDR_MSB8_SHIFT)
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#define PAX_DMA_MAX_SZ_PER_BD (512 * 1024)
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#define PAX_DMA_MEGA_LENGTH_MULTIPLE 16
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/* Maximum DMA block count supported per request */
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#define RM_V2_MAX_BLOCK_COUNT 4096
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#define MAX_BD_COUNT_PER_HEADER 30
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/*
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* Per-ring memory, with 8K & 4K alignment
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* Alignment may not be ensured by allocator
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* s/w need to allocate extra upto 8K to
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* ensure aligned memory space.
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*/
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#define PAX_DMA_PER_RING_ALLOC_SIZE (PAX_DMA_RM_CMPL_RING_SIZE * 2 + \
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PAX_DMA_NUM_BD_BUFFS * \
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PAX_DMA_RM_DESC_RING_SIZE)
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/* RM header desc field */
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struct rm_header {
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uint64_t opq : 16; /*pkt_id 15:0*/
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uint64_t bdf : 16; /*reserved 31:16*/
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uint64_t res1 : 4; /*res 32:35*/
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uint64_t bdcount : 5; /*bdcount 36:40*/
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uint64_t prot : 2; /*prot 41:42*/
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uint64_t res2 : 1; /*res :43:43*/
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uint64_t pcie_addr_msb : 8; /*pcie addr :44:51*/
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uint64_t res3 : 4; /*res :52:55*/
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uint64_t start : 1; /*S :56*/
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uint64_t end : 1; /*E:57*/
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uint64_t res4 : 1; /*res:58*/
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uint64_t toggle : 1; /*T:59*/
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uint64_t type : 4; /*type:60:63*/
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} __attribute__ ((__packed__));
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/* pcie desc field */
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struct pcie_desc {
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uint64_t pcie_addr_lsb : 56; /* pcie_addr_lsb 0:55*/
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uint64_t res1: 3; /*reserved 56:58*/
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uint64_t toggle : 1; /*T:59*/
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uint64_t type : 4; /*type:60:63*/
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} __attribute__ ((__packed__));
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/* src/dst desc field */
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struct src_dst_desc {
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uint64_t axi_addr : 44; /*axi_addr[43:0]*/
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uint64_t length : 15; /*length[44:58]*/
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uint64_t toggle : 1; /*T:59*/
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uint64_t type : 4; /*type:60:63*/
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} __attribute__ ((__packed__));
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struct next_ptr_desc {
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uint64_t addr : 44; /*Address 43:0*/
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uint64_t res1 : 15;/*Reserved*/
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uint64_t toggle : 1; /*Toggle Bit:59*/
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uint64_t type : 4;/*descriptor type 63:60*/
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} __attribute__ ((__packed__));
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#endif
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