136 lines
3.2 KiB
C
136 lines
3.2 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/timer/system_timer.h>
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#include <sys_clock.h>
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#include <spinlock.h>
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#include <soc.h>
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#define CYC_PER_TICK ((u32_t)((u64_t)sys_clock_hw_cycles_per_sec() \
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/ (u64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC))
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#define MAX_TICKS ((0xffffffffu - CYC_PER_TICK) / CYC_PER_TICK)
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#define MIN_DELAY 1000
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#define TICKLESS (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && \
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!IS_ENABLED(CONFIG_QEMU_TICKLESS_WORKAROUND))
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static struct k_spinlock lock;
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static u64_t last_count;
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static void set_mtimecmp(u64_t time)
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{
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volatile u32_t *r = (u32_t *)RISCV_MTIMECMP_BASE;
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/* Per spec, the RISC-V MTIME/MTIMECMP registers are 64 bit,
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* but are NOT internally latched for multiword transfers. So
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* we have to be careful about sequencing to avoid triggering
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* spurious interrupts: always set the high word to a max
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* value first.
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*/
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r[1] = 0xffffffff;
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r[0] = (u32_t)time;
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r[1] = (u32_t)(time >> 32);
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}
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static u64_t mtime(void)
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{
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volatile u32_t *r = (u32_t *)RISCV_MTIME_BASE;
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u32_t lo, hi;
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/* Likewise, must guard against rollover when reading */
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do {
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hi = r[1];
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lo = r[0];
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} while (r[1] != hi);
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return (((u64_t)hi) << 32) | lo;
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}
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static void timer_isr(void *arg)
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{
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ARG_UNUSED(arg);
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k_spinlock_key_t key = k_spin_lock(&lock);
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u64_t now = mtime();
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u32_t dticks = (u32_t)((now - last_count) / CYC_PER_TICK);
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last_count += dticks * CYC_PER_TICK;
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if (!TICKLESS) {
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u64_t next = last_count + CYC_PER_TICK;
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if ((s64_t)(next - now) < MIN_DELAY) {
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next += CYC_PER_TICK;
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}
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set_mtimecmp(next);
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}
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k_spin_unlock(&lock, key);
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z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1);
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}
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int z_clock_driver_init(struct device *device)
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{
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IRQ_CONNECT(RISCV_MACHINE_TIMER_IRQ, 0, timer_isr, NULL, 0);
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set_mtimecmp(mtime() + CYC_PER_TICK);
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irq_enable(RISCV_MACHINE_TIMER_IRQ);
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return 0;
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}
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void z_clock_set_timeout(s32_t ticks, bool idle)
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{
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ARG_UNUSED(idle);
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#if defined(CONFIG_TICKLESS_KERNEL) && !defined(CONFIG_QEMU_TICKLESS_WORKAROUND)
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/* RISCV has no idle handler yet, so if we try to spin on the
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* logic below to reset the comparator, we'll always bump it
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* forward to the "next tick" due to MIN_DELAY handling and
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* the interrupt will never fire! Just rely on the fact that
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* the OS gave us the proper timeout already.
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*/
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if (idle) {
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return;
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}
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ticks = ticks == K_FOREVER ? MAX_TICKS : ticks;
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ticks = MAX(MIN(ticks - 1, (s32_t)MAX_TICKS), 0);
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k_spinlock_key_t key = k_spin_lock(&lock);
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u64_t now = mtime();
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u32_t cyc = ticks * CYC_PER_TICK;
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/* Round up to next tick boundary. Note use of 32 bit math,
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* max_ticks is calibrated to permit this.
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*/
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cyc += (u32_t)(now - last_count) + (CYC_PER_TICK - 1);
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cyc = (cyc / CYC_PER_TICK) * CYC_PER_TICK;
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if ((s32_t)(cyc + last_count - now) < MIN_DELAY) {
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cyc += CYC_PER_TICK;
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}
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set_mtimecmp(cyc + last_count);
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k_spin_unlock(&lock, key);
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#endif
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}
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u32_t z_clock_elapsed(void)
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{
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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return 0;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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u32_t ret = ((u32_t)mtime() - (u32_t)last_count) / CYC_PER_TICK;
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k_spin_unlock(&lock, key);
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return ret;
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}
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u32_t z_timer_cycle_get_32(void)
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{
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return (u32_t)mtime();
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}
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