305 lines
7.0 KiB
C
305 lines
7.0 KiB
C
/*
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* Copyright (c) 2023 Frontgrade Gaisler AB
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Driver for GRLIB GRGPIO revision 2.
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* - iflag determine pending interrupt.
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* - interrupt map decides interrupt number if implemented.
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* - logic or/and/xor registers used when possible
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*/
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#define DT_DRV_COMPAT gaisler_grgpio
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include "gpio_grgpio.h"
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#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(gpio_grgpio2);
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struct cfg {
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struct gpio_driver_config common;
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volatile struct grgpio_regs *regs;
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int interrupt;
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};
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struct data {
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struct gpio_driver_data common;
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struct k_spinlock lock;
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sys_slist_t cb;
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uint32_t imask;
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uint32_t connected;
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int irqgen;
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};
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static void grgpio_isr(const struct device *dev);
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static int pin_configure(const struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct cfg *cfg = dev->config;
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struct data *data = dev->data;
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volatile struct grgpio_regs *regs = cfg->regs;
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uint32_t mask = 1 << pin;
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if (flags & GPIO_SINGLE_ENDED) {
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return -ENOTSUP;
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}
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if (flags == GPIO_DISCONNECTED) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_DIR_MASK) == (GPIO_INPUT | GPIO_OUTPUT)) {
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return -ENOTSUP;
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}
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if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
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return -ENOTSUP;
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}
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if (flags & GPIO_OUTPUT) {
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k_spinlock_key_t key;
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/*
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* Register operations are atomic, but do the sequence under
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* lock so it serializes.
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*/
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key = k_spin_lock(&data->lock);
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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regs->output_or = mask;
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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regs->output_and = ~mask;
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}
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regs->dir_or = mask;
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k_spin_unlock(&data->lock, key);
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} else {
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regs->dir_and = ~mask;
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}
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return 0;
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}
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static int port_get_raw(const struct device *dev, gpio_port_value_t *value)
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{
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const struct cfg *cfg = dev->config;
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*value = cfg->regs->data;
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return 0;
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}
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static int port_set_masked_raw(const struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct cfg *cfg = dev->config;
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struct data *data = dev->data;
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volatile struct grgpio_regs *regs = cfg->regs;
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uint32_t port_val;
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k_spinlock_key_t key;
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value &= mask;
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key = k_spin_lock(&data->lock);
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port_val = (regs->output & ~mask) | value;
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regs->output = port_val;
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct cfg *cfg = dev->config;
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volatile struct grgpio_regs *regs = cfg->regs;
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regs->output_or = pins;
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return 0;
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}
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static int port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct cfg *cfg = dev->config;
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volatile struct grgpio_regs *regs = cfg->regs;
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regs->output_and = ~pins;
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return 0;
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}
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static int port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct cfg *cfg = dev->config;
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volatile struct grgpio_regs *regs = cfg->regs;
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regs->output_xor = pins;
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return 0;
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}
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static uint32_t get_pending_int(const struct device *dev)
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{
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const struct cfg *cfg = dev->config;
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volatile struct grgpio_regs *regs = cfg->regs;
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return regs->iflag;
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}
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static int pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct cfg *cfg = dev->config;
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struct data *data = dev->data;
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volatile struct grgpio_regs *regs = cfg->regs;
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int ret = 0;
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const uint32_t mask = 1 << pin;
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uint32_t polmask;
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k_spinlock_key_t key;
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if ((mask & data->imask) == 0) {
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/* This pin can not generate interrupt */
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return -ENOTSUP;
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}
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if (mode != GPIO_INT_MODE_DISABLED) {
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if (trig == GPIO_INT_TRIG_LOW) {
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polmask = 0;
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} else if (trig == GPIO_INT_TRIG_HIGH) {
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polmask = mask;
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} else {
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return -ENOTSUP;
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}
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}
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key = k_spin_lock(&data->lock);
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if (mode == GPIO_INT_MODE_DISABLED) {
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regs->imask_and = ~mask;
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} else if (mode == GPIO_INT_MODE_LEVEL) {
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regs->imask_and = ~mask;
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regs->iedge &= ~mask;
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regs->ipol = (regs->ipol & ~mask) | polmask;
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regs->imask_or = mask;
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} else if (mode == GPIO_INT_MODE_EDGE) {
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regs->imask_and = ~mask;
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regs->iedge |= mask;
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regs->ipol = (regs->ipol & ~mask) | polmask;
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regs->imask_or = mask;
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} else {
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ret = -ENOTSUP;
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}
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k_spin_unlock(&data->lock, key);
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/* Remove old interrupt history for this pin. */
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regs->iflag = mask;
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int interrupt = cfg->interrupt;
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const int irqgen = data->irqgen;
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if (irqgen == 0) {
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interrupt += pin;
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} else if (irqgen == 1) {
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;
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} else if (irqgen < 32) {
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/* look up interrupt number in GRGPIO interrupt map */
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uint32_t val = regs->irqmap[pin/4];
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val >>= (3 - pin % 4) * 8;
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interrupt += (val & 0x1f);
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}
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if (interrupt && ((1 << interrupt) & data->connected) == 0) {
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irq_connect_dynamic(
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interrupt,
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0,
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(void (*)(const void *)) grgpio_isr,
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dev,
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0
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);
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irq_enable(interrupt);
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data->connected |= 1 << interrupt;
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}
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return ret;
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}
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static int manage_callback(const struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct data *data = dev->data;
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return gpio_manage_callback(&data->cb, callback, set);
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}
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static void grgpio_isr(const struct device *dev)
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{
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const struct cfg *cfg = dev->config;
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struct data *data = dev->data;
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volatile struct grgpio_regs *regs = cfg->regs;
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uint32_t pins;
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/* no locking needed when iflag is implemented */
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pins = regs->iflag;
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if (pins == 0) {
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return;
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}
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regs->iflag = pins;
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gpio_fire_callbacks(&data->cb, dev, pins);
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}
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static int grgpio_init(const struct device *dev)
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{
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const struct cfg *cfg = dev->config;
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struct data *data = dev->data;
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volatile struct grgpio_regs *regs = cfg->regs;
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data->irqgen = (regs->cap & GRGPIO_CAP_IRQGEN) >> GRGPIO_CAP_IRQGEN_BIT;
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regs->dir = 0;
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/* Mask all Interrupts */
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regs->imask = 0;
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/* Make IRQ Rising edge triggered default */
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regs->ipol = 0xffffffff;
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regs->iedge = 0xffffffff;
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regs->iflag = 0xffffffff;
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/* Read what I/O lines have IRQ support */
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data->imask = regs->ipol;
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return 0;
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}
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static const struct gpio_driver_api driver_api = {
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.pin_configure = pin_configure,
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.port_get_raw = port_get_raw,
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.port_set_masked_raw = port_set_masked_raw,
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.port_set_bits_raw = port_set_bits_raw,
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.port_clear_bits_raw = port_clear_bits_raw,
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.port_toggle_bits = port_toggle_bits,
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.pin_interrupt_configure = pin_interrupt_configure,
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.manage_callback = manage_callback,
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.get_pending_int = get_pending_int,
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};
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#define GRGPIO_INIT(n) \
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static const struct cfg cfg_##n = { \
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
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}, \
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.regs = (void *) DT_INST_REG_ADDR(n), \
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.interrupt = DT_INST_IRQN(n), \
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}; \
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static struct data data_##n; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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grgpio_init, \
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NULL, \
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&data_##n, \
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&cfg_##n, \
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POST_KERNEL, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&driver_api \
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);
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DT_INST_FOREACH_STATUS_OKAY(GRGPIO_INIT)
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