345 lines
9.3 KiB
Plaintext
345 lines
9.3 KiB
Plaintext
;*******************************************************************************
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; Copyright 2022 NXP *
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; SPDX-License-Identifier: Apache-2.0 *
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; *
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; Lauterbach Trace32 start-up script for S32Z27x / Cortex-R52 *
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; *
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; Parameters: *
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; - command operation to execute *
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; valid values: flash, debug *
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; default: debug *
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; - elfFile filepath of ELF to load *
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; - rtu Real-Time Unit (RTU) index *
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; valid values: 0, 1 *
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; default: 0 *
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; - core core index, relative to the RTU *
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; valid values: 0 to 3 *
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; default: 0 *
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; - lockstep set to "yes" to start the core in lock-step mode *
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; in Lockstep mode: *
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; - Core0 and Core2 (redundancy) operate as a lockstep pair *
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; - Core1 and Core3 (redundancy) operate as a lockstep pair *
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; default: yes *
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; - thumb set to "yes" to select the T32 instruction set at reset *
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; default: no *
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; *
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;*******************************************************************************
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ENTRY %LINE &args
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LOCAL &rtuStartAddr &cfgCoreAddr &coreId &rtuId &thumbBit &spltLckBit
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&command=STRing.SCANAndExtract("&args","command=","debug")
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&elfFile=STRing.SCANAndExtract("&args","elfFile=","")
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&rtu=STRing.SCANAndExtract("&args","rtu=","0")
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&core=STRing.SCANAndExtract("&args","core=","0")
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&lockstep=STRing.SCANAndExtract("&args","lockstep=","yes")
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&thumb=STRing.SCANAndExtract("&args","thumb=","no")
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IF ("&elfFile"=="")
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(
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PRINT %ERROR "Missing ELF file path"
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PLIST
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STOP
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ENDDO
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)
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IF (&rtu<0||&rtu>1)
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(
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PRINT %ERROR "Invalid rtu number: &rtu"
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PLIST
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STOP
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ENDDO
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)
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IF (&core<0||&core>3)
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(
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PRINT %ERROR "Invalid core number: &core"
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PLIST
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STOP
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ENDDO
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)
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; select ARMv8 instruction set at reset for all Cortex-R52 cores (CFG_CORE.THUMB bit)
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IF ("&thumb"=="yes")
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&thumbBit="1"
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ELSE
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&thumbBit="0"
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; select lock-step or split-lock mode (CFG_CORE.SPLT_LCK bit)
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IF ("&lockstep"=="yes")
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&spltLckBit="0"
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ELSE
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&spltLckBit="1"
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IF ("&rtu"=="0")
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(
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&rtuStartAddr = 0x79900000
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&cfgCoreAddr = 0x76120000
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)
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ELSE
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(
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&rtuStartAddr = 0x7D900000
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&cfgCoreAddr = 0x76920000
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)
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; Trace32 indexes are offset by 1
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&coreId=&core+1
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&rtuId=&rtu+1
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; Reset
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ON.ERROR.CONTinue
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JTAG.PIN NRESET 0
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JTAG.PIN NTRST 0
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WAIT 10ms
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JTAG.PIN NRESET 1
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JTAG.PIN NTRST 1
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WAIT 10ms
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ON.ERROR.DEFault
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; Initialize debugger
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SYStem.Down
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SYStem.CPU S32Z270-M33-SMU
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SYStem.CONFIG.DEBUGPORTTYPE JTAG
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SYStem.Option.DUALPORT ON
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SYStem.MemAccess DAP
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SYStem.JtagClock 40MHz
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Trace.DISable
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ETM.OFF
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ITM.OFF
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SYStem.Mode Prepare
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WAIT 1.s
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; Disable Functional Reset Escalation Threshold
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Data.Set EAXI:0x41850014 %LE %Long 0x0
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Data.Set EAXI:0x41850018 %LE %Long 0x0
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Data.Set EAXI:0x4185001C %LE %Long 0x0
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; Configure Miscellaneous Debug Module AP (MDM-AP) for RTU's
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Data.Set DP:0x1C100c0 %LE %Long 0x3cf3cf00
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Data.Set DP:0x1C100c8 %LE %Long 0x3cf3cf00
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; RTU subsystems out of reset logic
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GOSUB EnableRTU0
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GOSUB EnableRTU1
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; Init RTU SRAM
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DO ~~/demo/arm/hardware/s32z27/misc/s32z27_init_rtu&(rtu)_sram.cmm
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; Set reset value for TE bit and split-lock mode
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Data.Set EZAXI:&cfgCoreAddr %Long 0yXXXXxxxxXXXXxxxxXXXXxxxxXXXXx&(thumbBit)x&(spltLckBit) ; CFG_CORE
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; Write loop to self instruction
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Data.Set EAXI:&rtuStartAddr %Long 0xFFFEF7FF
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; Wake up core
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GOSUB EnableR52_&(rtu)_&(core)
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; Reconfigure debugger
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SYStem.CPU S32Z270-R52-RTU&(rtu)
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CORE.ASSIGN &coreId
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SYStem.CONFIG.CORE &coreId &rtuId
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SYStem.Option.DUALPORT ON
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SYStem.Option.ResBreak OFF
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SYStem.Option.EnReset OFF
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Trace.DISable
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ETM.OFF
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STM.OFF
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WAIT 200ms
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SYStem.Attach
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IF STATE.RUN()
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Break
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; Load application to SRAM, running from flash is not yet supported
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Data.LOAD.Elf &elfFile EAXI:
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SYStem.MemAccess.AXI
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SYStem.CONFIG.AHBAP1.Base DP:0x1C80000
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SYStem.CONFIG.APBAP1.Base DP:0x1C30000
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SYStem.CONFIG.AXIAP1.Base DP:0x1C21000
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Register.Set PC __start
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IF ("&command"=="flash")
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(
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; Execute the application and quit
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Go
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QUIT
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)
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ELSE
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(
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; Setup minimal debug environment
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WinCLEAR
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SETUP.Var.%SpotLight
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WinPOS 0. 0. 120. 30.
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List.auto
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WinPOS 125. 0. 80. 10.
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Frame.view
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WinPOS 125. 18.
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Register.view /SpotLight
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)
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ENDDO
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EnableRTU0:
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(
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; RTU0 subsystem out of reset logic (MC_ME)
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Data.Set EAXI:0x41900300 %LE %Long 0x5
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Data.Set EAXI:0x41900304 %LE %Long 0x1
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Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
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Data.Set EAXI:0x41900000 %LE %Long 0xA50F
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WAIT 100ms
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; Deactivate RTU fencing logic (GPR3)
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Data.Set EAXI:0x4186005c %LE %Long 0x0
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; Enable the interconnect interface of reset domain
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Data.Set EAXI:0x41890004 %LE %Long 0x80000000
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Data.Set EAXI:0x41890004 %LE %Long 0x80000007
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; Assert reset (RGM)
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Data.Set EAXI:0x41850048 %LE %Long 0x1E
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; Clear OSSE bit and set clock update (MC_ME)
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Data.Set EAXI:0x41900300 %LE %Long 0x1
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Data.Set EAXI:0x41900304 %LE %Long 0x4
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Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
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Data.Set EAXI:0x41900000 %LE %Long 0xA50F
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WAIT 200ms
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RETURN
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)
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EnableRTU1:
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(
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; RTU1 subsystem out of reset logic (MC_ME)
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Data.Set EAXI:0x41900500 %LE %Long 0x5
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Data.Set EAXI:0x41900504 %LE %Long 0x1
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Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
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Data.Set EAXI:0x41900000 %LE %Long 0xA50F
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WAIT 100ms
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; Deactivate RTU fencing logic (GPR3)
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Data.Set EAXI:0x41860064 %LE %Long 0x0
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; Enable the interconnect interface of reset domain
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Data.Set EAXI:0x418A0004 %LE %Long 0x80000000
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Data.Set EAXI:0x418A0004 %LE %Long 0x80000007
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; Assert reset (RGM)
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Data.Set EAXI:0x41850050 %LE %Long 0x1E
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; Clear OSSE bit and set clock update (MC_ME)
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Data.Set EAXI:0x41900500 %LE %Long 0x1
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Data.Set EAXI:0x41900504 %LE %Long 0x4
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Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
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Data.Set EAXI:0x41900000 %LE %Long 0xA50F
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WAIT 200ms
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; Enable RTU1 NIC
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Data.Set EAXI:0x75400000 %LE %Long 0x2 ; RTUM_NIC
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Data.Set EAXI:0x75500000 %LE %Long 0x2 ; RTUF_NIC
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Data.Set EAXI:0x75600000 %LE %Long 0x2 ; RTUP_NIC
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Data.Set EAXI:0x75700000 %LE %Long 0x2 ; RTUE_NIC
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RETURN
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)
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; EnableR52_<core>_<rtu> - routines for waking up the RTU cores:
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; - set boot address (MC_ME_PRTNy_COREx_ADDR)
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; - enable core clock
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; - trigger the clock update
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; - store key for starting the hw process
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; - force core reset
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EnableR52_0_0:
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(
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Data.Set EAXI:0x4190034C %LE %Long &rtuStartAddr
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Data.Set EAXI:0x41900340 %LE %Long 0x1
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Data.Set EAXI:0x41900344 %LE %Long 0x1
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Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
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Data.Set EAXI:0x41900000 %LE %Long 0xA50F
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Data.Set EAXI:0x41850048 %LE %Long 0x1C
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RETURN
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)
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EnableR52_0_1:
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(
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Data.Set EAXI:0x4190036C %LE %Long &rtuStartAddr
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Data.Set EAXI:0x41900360 %LE %Long 0x1
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Data.Set EAXI:0x41900364 %LE %Long 0x1
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Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
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Data.Set EAXI:0x41900000 %LE %Long 0xA50F
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Data.Set EAXI:0x41850048 %LE %Long 0x18
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RETURN
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)
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EnableR52_0_2:
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(
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Data.Set EAXI:0x4190038C %LE %Long &rtuStartAddr
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Data.Set EAXI:0x41900380 %LE %Long 0x1
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Data.Set EAXI:0x41900384 %LE %Long 0x1
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Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
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Data.Set EAXI:0x41900000 %LE %Long 0xA50F
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Data.Set EAXI:0x41850048 %LE %Long 0x10
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RETURN
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)
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EnableR52_0_3:
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(
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Data.Set EAXI:0x419003AC %LE %Long &rtuStartAddr
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Data.Set EAXI:0x419003A0 %LE %Long 0x1
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Data.Set EAXI:0x419003A4 %LE %Long 0x1
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Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
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Data.Set EAXI:0x41900000 %LE %Long 0xA50F
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Data.Set EAXI:0x41850048 %LE %Long 0x0
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RETURN
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)
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EnableR52_1_0:
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(
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Data.Set EAXI:0x4190054C %LE %Long &rtuStartAddr
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Data.Set EAXI:0x41900540 %LE %Long 0x1
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Data.Set EAXI:0x41900544 %LE %Long 0x1
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Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
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Data.Set EAXI:0x41900000 %LE %Long 0xA50F
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Data.Set EAXI:0x41850050 %LE %Long 0x1C
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RETURN
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)
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EnableR52_1_1:
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(
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Data.Set EAXI:0x4190056C %LE %Long &rtuStartAddr
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Data.Set EAXI:0x41900560 %LE %Long 0x1
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Data.Set EAXI:0x41900564 %LE %Long 0x1
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Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
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Data.Set EAXI:0x41900000 %LE %Long 0xA50F
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Data.Set EAXI:0x41850050 %LE %Long 0x18
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RETURN
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)
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EnableR52_1_2:
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(
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Data.Set EAXI:0x4190058C %LE %Long &rtuStartAddr
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Data.Set EAXI:0x41900580 %LE %Long 0x1
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Data.Set EAXI:0x41900584 %LE %Long 0x1
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Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
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Data.Set EAXI:0x41900000 %LE %Long 0xA50F
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Data.Set EAXI:0x41850050 %LE %Long 0x10
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RETURN
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)
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EnableR52_1_3:
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(
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Data.Set EAXI:0x419005A0 %LE %Long 0x1
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Data.Set EAXI:0x419005A4 %LE %Long 0x1
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Data.Set EAXI:0x41900000 %LE %Long 0x5AF0
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Data.Set EAXI:0x41900000 %LE %Long 0xA50F
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Data.Set EAXI:0x419005AC %LE %Long &rtuStartAddr
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Data.Set EAXI:0x41850050 %LE %Long 0x0
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RETURN
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)
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