396 lines
9.0 KiB
C
396 lines
9.0 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file Driver for the MMIO-based GPIO driver.
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*/
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#include <nanokernel.h>
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#include <gpio.h>
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#include "gpio-mmio.h"
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#if defined(CONFIG_GPIO_MMIO_0_ACCESS_MM) \
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|| defined(CONFIG_GPIO_MMIO_1_ACCESS_MM)
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static uint32_t _mm_set_bit(uint32_t addr, uint32_t bit, uint32_t value)
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{
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if (!value) {
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sys_clear_bit(addr, bit);
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} else {
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sys_set_bit(addr, bit);
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}
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return 0;
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}
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static uint32_t _mm_read(uint32_t addr, uint32_t bit, uint32_t value)
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{
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ARG_UNUSED(bit);
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ARG_UNUSED(value);
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return sys_read32(addr);
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}
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static uint32_t _mm_write(uint32_t addr, uint32_t bit, uint32_t value)
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{
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ARG_UNUSED(bit);
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sys_write32(value, addr);
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return 0;
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}
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#endif /* if direct memory access is needed */
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#if defined(CONFIG_GPIO_MMIO_0_ACCESS_IO) \
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|| defined(CONFIG_GPIO_MMIO_1_ACCESS_IO)
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static uint32_t _io_set_bit(uint32_t addr, uint32_t bit, uint32_t value)
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{
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uint32_t bit_mask = (1 << bit);
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uint32_t tmp;
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tmp = sys_in32(addr);
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tmp &= ~bit_mask;
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tmp |= (value << bit) & bit_mask;
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sys_out32(tmp, addr);
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return 0;
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}
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static uint32_t _io_read(uint32_t addr, uint32_t bit, uint32_t value)
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{
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ARG_UNUSED(bit);
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ARG_UNUSED(value);
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return sys_in32(addr);
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}
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static uint32_t _io_write(uint32_t addr, uint32_t bit, uint32_t value)
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{
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ARG_UNUSED(bit);
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sys_out32(value, addr);
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return 0;
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}
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#endif /* if io port access is needed */
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/**
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* @brief Configurate pin or port
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*
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* @param dev Device struct
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* @param access_op Access operation (pin or port)
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* @param pin The pin number
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* @param flags Flags of pin or port
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*
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* @return DEV_OK if successful, failed otherwise
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*/
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static int gpio_mmio_config(struct device *dev, int access_op,
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uint32_t pin, int flags)
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{
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const struct gpio_mmio_config * const cfg =
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dev->config->config_info;
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uint32_t value = 0;
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/* Setup direction register */
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if (!cfg->reg.dir) {
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return DEV_INVALID_CONF;
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}
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if (cfg->cfg_flags & GPIO_MMIO_CFG_DIR_MASK) {
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/* Direction register is inverse
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* INV: 0 - pin is input, 1 - pin is output
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*/
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
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value = 0x0;
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} else {
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value = 0xFFFFFFFF;
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}
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} else {
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/* Direction register is normal.
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* NORMAL: 0 - pin is output, 1 - pin is input
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*/
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
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value = 0xFFFFFFFF;
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} else {
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value = 0x0;
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}
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}
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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cfg->access.set_bit(cfg->reg.dir, pin, value);
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break;
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case GPIO_ACCESS_BY_PORT:
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cfg->access.write(cfg->reg.dir, 0, value);
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break;
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default:
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return DEV_INVALID_OP;
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}
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/*
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* Enable the GPIO pin(s), since the direction is
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* also being setup. This indicates pin(s) is being used.
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*
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* This is not really necessary, so don't fail if
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* register is not defined.
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*/
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if (!cfg->reg.en) {
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return DEV_OK;
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}
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if (cfg->cfg_flags & GPIO_MMIO_CFG_EN_MASK) {
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/* INV: 0 - enable, 1 - disable */
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value = 0x0;
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} else {
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/* NORMAL: 0 - disable, 1 - enable */
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value = 0xFFFFFFFF;
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}
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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cfg->access.set_bit(cfg->reg.en, pin, value);
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break;
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case GPIO_ACCESS_BY_PORT:
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cfg->access.write(cfg->reg.en, 0, value);
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break;
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default:
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return DEV_INVALID_OP;
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}
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return DEV_OK;
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}
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/**
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* @brief Set the pin or port output
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*
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* @param dev Device struct
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* @param access_op Access operation (pin or port)
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* @param pin The pin number
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* @param value Value to set (0 or 1)
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*
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* @return DEV_OK if successful, failed otherwise
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*/
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static int gpio_mmio_write(struct device *dev, int access_op,
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uint32_t pin, uint32_t value)
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{
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const struct gpio_mmio_config * const cfg =
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dev->config->config_info;
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if (!cfg->reg.output) {
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return DEV_INVALID_CONF;
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}
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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cfg->access.set_bit(cfg->reg.output, pin, value);
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break;
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case GPIO_ACCESS_BY_PORT:
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cfg->access.write(cfg->reg.output, 0, value);
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break;
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default:
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return DEV_INVALID_OP;
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}
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return DEV_OK;
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}
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/**
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* @brief Read the pin or port status
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*
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* @param dev Device struct
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* @param access_op Access operation (pin or port)
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* @param pin The pin number
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* @param value Value of input pin(s)
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*
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* @return DEV_OK if successful, failed otherwise
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*/
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static int gpio_mmio_read(struct device *dev, int access_op,
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uint32_t pin, uint32_t *value)
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{
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const struct gpio_mmio_config * const cfg =
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dev->config->config_info;
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if (!cfg->reg.input) {
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return DEV_INVALID_CONF;
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}
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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*value = cfg->access.read(cfg->reg.input, 0, 0);
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*value &= (1 << pin) >> pin;
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break;
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case GPIO_ACCESS_BY_PORT:
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*value = cfg->access.read(cfg->reg.input, 0, 0);
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break;
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default:
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return DEV_INVALID_OP;
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}
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return DEV_OK;
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}
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static int gpio_mmio_set_callback(struct device *dev,
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gpio_callback_t callback)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(callback);
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return DEV_INVALID_OP;
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}
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static int gpio_mmio_enable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(access_op);
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ARG_UNUSED(pin);
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return DEV_INVALID_OP;
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}
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static int gpio_mmio_disable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(access_op);
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ARG_UNUSED(pin);
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return DEV_INVALID_OP;
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}
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static int gpio_mmio_suspend_port(struct device *dev)
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{
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ARG_UNUSED(dev);
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return DEV_INVALID_OP;
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}
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static int gpio_mmio_resume_port(struct device *dev)
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{
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ARG_UNUSED(dev);
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return DEV_INVALID_OP;
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}
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static struct gpio_driver_api gpio_mmio_drv_api_funcs = {
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.config = gpio_mmio_config,
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.write = gpio_mmio_write,
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.read = gpio_mmio_read,
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.set_callback = gpio_mmio_set_callback,
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.enable_callback = gpio_mmio_enable_callback,
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.disable_callback = gpio_mmio_disable_callback,
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.suspend = gpio_mmio_suspend_port,
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.resume = gpio_mmio_resume_port,
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};
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/**
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* @brief Initialization function of MMIO
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*
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* @param dev Device struct
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* @return DEV_OK if successful, failed otherwise.
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*/
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int gpio_mmio_init(struct device *dev)
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{
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dev->driver_api = &gpio_mmio_drv_api_funcs;
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return DEV_OK;
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}
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/* Initialization for MMIO_0 */
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#ifdef CONFIG_GPIO_MMIO_0
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#include <device.h>
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#include <init.h>
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static struct gpio_mmio_config gpio_mmio_0_cfg = {
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.cfg_flags = CONFIG_GPIO_MMIO_0_CFG,
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.reg.en = CONFIG_GPIO_MMIO_0_EN,
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.reg.dir = CONFIG_GPIO_MMIO_0_DIR,
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.reg.input = CONFIG_GPIO_MMIO_0_INPUT,
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.reg.output = CONFIG_GPIO_MMIO_0_OUTPUT,
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#ifdef CONFIG_GPIO_MMIO_0_ACCESS_IO
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.access.set_bit = _io_set_bit,
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.access.read = _io_read,
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.access.write = _io_write,
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#else /* below is for CONFIG_GPIO_MMIO_0_ACCESS_MM=y or else */
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.access.set_bit = _mm_set_bit,
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.access.read = _mm_read,
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.access.write = _mm_write,
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#endif
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};
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DECLARE_DEVICE_INIT_CONFIG(gpio_mmio_0,
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CONFIG_GPIO_MMIO_0_DEV_NAME,
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gpio_mmio_init,
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&gpio_mmio_0_cfg);
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pre_kernel_late_init(gpio_mmio_0, (void *)0);
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#endif /* CONFIG_GPIO_MMIO_0 */
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/* Initialization for MMIO_1 */
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#ifdef CONFIG_GPIO_MMIO_1
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#include <device.h>
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#include <init.h>
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static struct gpio_mmio_config gpio_mmio_1_cfg = {
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.cfg_flags = CONFIG_GPIO_MMIO_0_CFG,
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.reg.en = CONFIG_GPIO_MMIO_1_EN,
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.reg.dir = CONFIG_GPIO_MMIO_1_DIR,
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.reg.input = CONFIG_GPIO_MMIO_1_INPUT,
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.reg.output = CONFIG_GPIO_MMIO_1_OUTPUT,
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#ifdef CONFIG_GPIO_MMIO_1_ACCESS_IO
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.access.set_bit = _io_set_bit,
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.access.read = _io_read,
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.access.write = _io_write,
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#else /* below is for CONFIG_GPIO_MMIO_1_ACCESS_MM=y or else */
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.access.set_bit = _mm_set_bit,
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.access.read = _mm_read,
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.access.write = _mm_write,
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#endif
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};
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DECLARE_DEVICE_INIT_CONFIG(gpio_mmio_1,
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CONFIG_GPIO_MMIO_1_DEV_NAME,
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gpio_mmio_init,
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&gpio_mmio_1_cfg);
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pre_kernel_late_init(gpio_mmio_1, (void *)0);
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#endif /* CONFIG_GPIO_MMIO_1 */
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