221 lines
5.2 KiB
C
221 lines
5.2 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <nanokernel.h>
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#include <sys_io.h>
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#include <stdio.h>
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#include <rtc.h>
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#include <init.h>
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#include <clock_control.h>
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#include "board.h"
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#include "rtc_dw.h"
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#define RTC_CLK_DIV_DEF_MASK (0xFFFFFF83)
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#define CCU_RTC_CLK_DIV_EN (2)
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#ifdef RTC_DW_INT_MASK
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static inline void _rtc_dw_int_unmask(void)
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{
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sys_write32(sys_read32(RTC_DW_INT_MASK) & INT_UNMASK_IA,
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RTC_DW_INT_MASK);
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}
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#else
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#define _rtc_dw_int_unmask()
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#endif
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#ifdef CONFIG_RTC_DW_CLOCK_GATE
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static inline void _rtc_dw_clock_config(struct device *dev)
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{
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char *drv = CONFIG_RTC_DW_CLOCK_GATE_DRV_NAME;
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struct device *clk;
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clk = device_get_binding(drv);
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if (clk) {
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struct rtc_dw_runtime *context = dev->driver_data;
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context->clock = clk;
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}
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}
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static inline void _rtc_dw_clock_on(struct device *dev)
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{
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struct rtc_dw_dev_config *config = dev->config->config_info;
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struct rtc_dw_runtime *context = dev->driver_data;
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clock_control_on(context->clock, config->clock_data);
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}
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static inline void _rtc_dw_clock_off(struct device *dev)
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{
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struct rtc_dw_dev_config *config = dev->config->config_info;
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struct rtc_dw_runtime *context = dev->driver_data;
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clock_control_off(context->clock, config->clock_data);
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}
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#else
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#define _rtc_dw_clock_config(...)
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#define _rtc_dw_clock_on(...)
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#define _rtc_dw_clock_off(...)
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#endif
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static void rtc_dw_set_div(const enum clk_rtc_div div)
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{
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/* set default division mask */
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uint32_t reg =
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sys_read32(CLOCK_SYSTEM_CLOCK_CONTROL) & RTC_CLK_DIV_DEF_MASK;
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reg |= (div << CCU_RTC_CLK_DIV_OFFSET);
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sys_write32(reg, CLOCK_SYSTEM_CLOCK_CONTROL);
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/* CLK Div en bit must be written from 0 -> 1 to apply new value */
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sys_set_bit(CLOCK_SYSTEM_CLOCK_CONTROL, CCU_RTC_CLK_DIV_EN);
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}
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/**
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* @brief Function to enable clock gating for the RTC
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* @return N/A
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*/
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static void rtc_dw_enable(struct device *dev)
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{
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_rtc_dw_clock_on(dev);
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}
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/**
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* @brief Function to disable clock gating for the RTC
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* @return N/A
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*/
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static void rtc_dw_disable(struct device *dev)
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{
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_rtc_dw_clock_off(dev);
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}
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/**
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* @brief RTC alarm ISR
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*
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* calls a user defined callback
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*
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* @return N/A
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*/
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void rtc_dw_isr(void *arg)
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{
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struct device *dev = arg;
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struct rtc_dw_dev_config *rtc_dev = dev->config->config_info;
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struct rtc_dw_runtime *context = dev->driver_data;
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/* Disable RTC interrupt */
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sys_clear_bit(rtc_dev->base_address + RTC_CCR, 0);
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if (context->rtc_dw_cb_fn) {
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context->rtc_dw_cb_fn(dev);
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}
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/* clear interrupt */
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sys_read32(rtc_dev->base_address + RTC_EOI);
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}
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/**
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* @brief Sets an RTC alarm
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* @param alarm_val Alarm value
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* @return 0 on success
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*/
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static int rtc_dw_set_alarm(struct device *dev, const uint32_t alarm_val)
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{
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struct rtc_dw_dev_config *rtc_dev = dev->config->config_info;
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sys_set_bit(rtc_dev->base_address + RTC_CCR, 0);
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sys_write32(alarm_val, rtc_dev->base_address + RTC_CMR);
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return 0;
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}
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/**
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* @brief Function to configure the RTC
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* @param config pointer to a RTC configuration structure
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* @return 0 on success
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*/
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static int rtc_dw_set_config(struct device *dev, struct rtc_config *config)
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{
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struct rtc_dw_dev_config *rtc_dev = dev->config->config_info;
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struct rtc_dw_runtime *context = dev->driver_data;
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/* Set RTC divider - 32768 / 32.768 khz = 1 second. */
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rtc_dw_set_div(RTC_DIVIDER);
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/* set initial RTC value */
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sys_write32(config->init_val, rtc_dev->base_address + RTC_CLR);
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/* clear any pending interrupts */
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sys_read32(rtc_dev->base_address + RTC_EOI);
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context->rtc_dw_cb_fn = config->cb_fn;
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if (config->alarm_enable) {
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rtc_dw_set_alarm(dev, config->alarm_val);
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} else {
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sys_clear_bit(rtc_dev->base_address + RTC_CCR, 0);
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}
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return 0;
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}
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/**
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* @brief Read current RTC value
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* @return current rtc value
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*/
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static uint32_t rtc_dw_read(struct device *dev)
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{
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struct rtc_dw_dev_config *rtc_dev = dev->config->config_info;
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return sys_read32(rtc_dev->base_address + RTC_CCVR);
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}
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static struct rtc_driver_api api_funcs = {
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.set_config = rtc_dw_set_config,
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.read = rtc_dw_read,
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.enable = rtc_dw_enable,
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.disable = rtc_dw_disable,
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.set_alarm = rtc_dw_set_alarm,
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};
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int rtc_dw_init(struct device *dev);
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struct rtc_dw_runtime rtc_runtime;
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struct rtc_dw_dev_config rtc_dev = {
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.base_address = RTC_DW_BASE_ADDR,
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#ifdef CONFIG_RTC_DW_CLOCK_GATE
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.clock_data = UINT_TO_POINTER(CONFIG_RTC_DW_CLOCK_GATE_SUBSYS),
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#endif
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};
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DEVICE_AND_API_INIT(rtc, CONFIG_RTC_DRV_NAME, &rtc_dw_init,
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&rtc_runtime, &rtc_dev,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&api_funcs);
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int rtc_dw_init(struct device *dev)
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{
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IRQ_CONNECT(RTC_DW_IRQ, CONFIG_RTC_DW_IRQ_PRI, rtc_dw_isr,
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DEVICE_GET(rtc), 0);
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irq_enable(RTC_DW_IRQ);
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_rtc_dw_int_unmask();
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_rtc_dw_clock_config(dev);
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return 0;
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}
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