93 lines
2.7 KiB
C
93 lines
2.7 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file SoC configuration macros for the STM32F103 family processors.
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*
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* Based on reference manual:
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* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
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* advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 3.3: Memory Map
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*/
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#ifndef _STM32F1_SOC_H_
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#define _STM32F1_SOC_H_
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/* peripherals start address */
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#define PERIPH_BASE 0x40000000
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/* use naming consistent with STMF10x Peripherals Library */
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#define APB1PERIPH_BASE PERIPH_BASE
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
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/* UART */
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#define USART1_ADDR (APB2PERIPH_BASE + 0x3800)
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#define USART2_ADDR (APB1PERIPH_BASE + 0x4400)
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#define USART3_ADDR (APB1PERIPH_BASE + 0x4800)
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/* Reset and Clock Control */
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#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
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#define GPIO_REG_SIZE 0x400
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#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
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#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
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#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
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#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
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#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
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#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
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#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
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/* base address for where GPIO registers start */
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#define GPIO_PORTS_BASE (GPIOA_BASE)
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/* EXTI */
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#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
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/* AFIO */
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#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
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/* IWDG */
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#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
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/* FLASH */
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#define FLASH_BASE (AHBPERIPH_BASE + 0x2000)
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#ifndef _ASMLANGUAGE
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#include <device.h>
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#include <misc/util.h>
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#include <drivers/rand32.h>
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/* IO pin functions */
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enum stm32f10x_pin_config_mode {
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STM32F10X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
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STM32F10X_PIN_CONFIG_BIAS_PULL_UP,
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STM32F10X_PIN_CONFIG_BIAS_PULL_DOWN,
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STM32F10X_PIN_CONFIG_ANALOG,
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STM32F10X_PIN_CONFIG_DRIVE_OPEN_DRAIN,
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STM32F10X_PIN_CONFIG_DRIVE_PUSH_PULL,
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STM32F10X_PIN_CONFIG_AF_PUSH_PULL,
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STM32F10X_PIN_CONFIG_AF_OPEN_DRAIN,
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};
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#include "soc_irq.h"
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#endif /* !_ASMLANGUAGE */
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#endif /* _STM32F1_SOC_H_ */
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