256 lines
6.2 KiB
C
256 lines
6.2 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <kernel_structs.h>
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#include <misc/printk.h>
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#include <inttypes.h>
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#include <logging/log_ctrl.h>
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const NANO_ESF _default_esf = {
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad
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};
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/**
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*
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* @brief Kernel fatal error handler
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*
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* This routine is called when a fatal error condition is detected by either
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* hardware or software.
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*
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* The caller is expected to always provide a usable ESF. In the event that the
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* fatal error does not have a hardware generated ESF, the caller should either
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* create its own or call _Fault instead.
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*
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* @param reason the reason that the handler was called
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* @param pEsf pointer to the exception stack frame
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*
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* @return This function does not return.
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*/
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FUNC_NORETURN void z_NanoFatalErrorHandler(unsigned int reason,
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const NANO_ESF *esf)
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{
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LOG_PANIC();
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#ifdef CONFIG_PRINTK
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switch (reason) {
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case _NANO_ERR_CPU_EXCEPTION:
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case _NANO_ERR_SPURIOUS_INT:
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break;
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case _NANO_ERR_ALLOCATION_FAIL:
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printk("**** Kernel Allocation Failure! ****\n");
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break;
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case _NANO_ERR_KERNEL_OOPS:
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printk("***** Kernel OOPS! *****\n");
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break;
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case _NANO_ERR_KERNEL_PANIC:
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printk("***** Kernel Panic! *****\n");
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break;
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#ifdef CONFIG_STACK_SENTINEL
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case _NANO_ERR_STACK_CHK_FAIL:
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printk("***** Stack overflow *****\n");
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break;
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#endif
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default:
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printk("**** Unknown Fatal Error %u! ****\n", reason);
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break;
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}
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/* Subtract 4 from EA since we added 4 earlier so that the faulting
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* instruction isn't retried.
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*
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* TODO: Only caller-saved registers get saved upon exception entry.
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* We may want to introduce a config option to save and dump all
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* registers, at the expense of some stack space.
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*/
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printk("Current thread ID: %p\n"
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"Faulting instruction: 0x%x\n"
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" r1: 0x%x r2: 0x%x r3: 0x%x r4: 0x%x\n"
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" r5: 0x%x r6: 0x%x r7: 0x%x r8: 0x%x\n"
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" r9: 0x%x r10: 0x%x r11: 0x%x r12: 0x%x\n"
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" r13: 0x%x r14: 0x%x r15: 0x%x ra: 0x%x\n"
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"estatus: %x\n", k_current_get(), esf->instr - 4,
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esf->r1, esf->r2, esf->r3, esf->r4,
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esf->r5, esf->r6, esf->r7, esf->r8,
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esf->r9, esf->r10, esf->r11, esf->r12,
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esf->r13, esf->r14, esf->r15, esf->ra,
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esf->estatus);
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#endif
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z_SysFatalErrorHandler(reason, esf);
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}
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#if defined(CONFIG_EXTRA_EXCEPTION_INFO) && defined(CONFIG_PRINTK) \
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&& defined(ALT_CPU_HAS_EXTRA_EXCEPTION_INFO)
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static char *cause_str(u32_t cause_code)
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{
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switch (cause_code) {
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case 0:
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return "reset";
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case 1:
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return "processor-only reset request";
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case 2:
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return "interrupt";
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case 3:
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return "trap";
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case 4:
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return "unimplemented instruction";
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case 5:
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return "illegal instruction";
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case 6:
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return "misaligned data address";
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case 7:
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return "misaligned destination address";
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case 8:
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return "division error";
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case 9:
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return "supervisor-only instruction address";
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case 10:
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return "supervisor-only instruction";
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case 11:
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return "supervisor-only data address";
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case 12:
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return "TLB miss";
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case 13:
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return "TLB permission violation (execute)";
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case 14:
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return "TLB permission violation (read)";
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case 15:
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return "TLB permission violation (write)";
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case 16:
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return "MPU region violation (instruction)";
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case 17:
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return "MPU region violation (data)";
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case 18:
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return "ECC TLB error";
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case 19:
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return "ECC fetch error (instruction)";
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case 20:
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return "ECC register file error";
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case 21:
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return "ECC data error";
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case 22:
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return "ECC data cache writeback error";
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case 23:
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return "bus instruction fetch error";
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case 24:
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return "bus data region violation";
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default:
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return "unknown";
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}
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}
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#endif
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FUNC_NORETURN void _Fault(const NANO_ESF *esf)
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{
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#ifdef CONFIG_PRINTK
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/* Unfortunately, completely unavailable on Nios II/e cores */
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#ifdef ALT_CPU_HAS_EXTRA_EXCEPTION_INFO
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u32_t exc_reg, badaddr_reg, eccftl;
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enum nios2_exception_cause cause;
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exc_reg = z_nios2_creg_read(NIOS2_CR_EXCEPTION);
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/* Bit 31 indicates potentially fatal ECC error */
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eccftl = (exc_reg & NIOS2_EXCEPTION_REG_ECCFTL_MASK) != 0U;
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/* Bits 2-6 contain the cause code */
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cause = (exc_reg & NIOS2_EXCEPTION_REG_CAUSE_MASK)
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>> NIOS2_EXCEPTION_REG_CAUSE_OFST;
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printk("Exception cause: %d ECCFTL: 0x%x\n", cause, eccftl);
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#if CONFIG_EXTRA_EXCEPTION_INFO
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printk("reason: %s\n", cause_str(cause));
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#endif
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if (BIT(cause) & NIOS2_BADADDR_CAUSE_MASK) {
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badaddr_reg = z_nios2_creg_read(NIOS2_CR_BADADDR);
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printk("Badaddr: 0x%x\n", badaddr_reg);
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}
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#endif /* ALT_CPU_HAS_EXTRA_EXCEPTION_INFO */
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#endif /* CONFIG_PRINTK */
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z_NanoFatalErrorHandler(_NANO_ERR_CPU_EXCEPTION, esf);
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}
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/**
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*
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* @brief Fatal error handler
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*
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* This routine implements the corrective action to be taken when the system
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* detects a fatal error.
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*
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* This sample implementation attempts to abort the current thread and allow
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* the system to continue executing, which may permit the system to continue
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* functioning with degraded capabilities.
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*
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* System designers may wish to enhance or substitute this sample
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* implementation to take other actions, such as logging error (or debug)
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* information to a persistent repository and/or rebooting the system.
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*
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* @param reason the fatal error reason
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* @param pEsf pointer to exception stack frame
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*
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* @return N/A
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*/
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FUNC_NORETURN __weak void z_SysFatalErrorHandler(unsigned int reason,
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const NANO_ESF *pEsf)
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{
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ARG_UNUSED(pEsf);
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#if !defined(CONFIG_SIMPLE_FATAL_ERROR_HANDLER)
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#ifdef CONFIG_STACK_SENTINEL
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if (reason == _NANO_ERR_STACK_CHK_FAIL) {
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goto hang_system;
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}
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#endif
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if (reason == _NANO_ERR_KERNEL_PANIC) {
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goto hang_system;
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}
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if (k_is_in_isr() || z_is_thread_essential()) {
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printk("Fatal fault in %s! Spinning...\n",
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k_is_in_isr() ? "ISR" : "essential thread");
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goto hang_system;
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}
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printk("Fatal fault in thread %p! Aborting.\n", _current);
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k_thread_abort(_current);
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hang_system:
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#else
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ARG_UNUSED(reason);
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#endif
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#ifdef ALT_CPU_HAS_DEBUG_STUB
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z_nios2_break();
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#endif
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for (;;) {
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k_cpu_idle();
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}
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CODE_UNREACHABLE;
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}
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