79 lines
1.8 KiB
C
79 lines
1.8 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Stack helpers for Cortex-M CPUs
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*
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* Stack helper functions.
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*/
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#ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_STACK_H_
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#define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_STACK_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _ASMLANGUAGE
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/* nothing */
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#else
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#include <arch/arm/cortex_m/cmsis.h>
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extern K_THREAD_STACK_DEFINE(_interrupt_stack, CONFIG_ISR_STACK_SIZE);
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/**
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*
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* @brief Setup interrupt stack
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*
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* On Cortex-M, the interrupt stack is registered in the MSP (main stack
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* pointer) register, and switched to automatically when taking an exception.
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void z_InterruptStackSetup(void)
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{
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#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT) && \
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defined(CONFIG_USERSPACE)
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u32_t msp = (u32_t)(Z_THREAD_STACK_BUFFER(_interrupt_stack) +
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CONFIG_ISR_STACK_SIZE - MPU_GUARD_ALIGN_AND_SIZE);
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#else
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u32_t msp = (u32_t)(Z_THREAD_STACK_BUFFER(_interrupt_stack) +
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CONFIG_ISR_STACK_SIZE);
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#endif
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__set_MSP(msp);
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#if defined(CONFIG_BUILTIN_STACK_GUARD)
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#if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM)
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__set_MSPLIM((u32_t)_interrupt_stack);
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#else
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#error "Built-in MSP limit checks not supported by HW"
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#endif
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#endif /* CONFIG_BUILTIN_STACK_GUARD */
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#if defined(CONFIG_STACK_ALIGN_DOUBLE_WORD)
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/* Enforce double-word stack alignment on exception entry
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* for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
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* of ARM Cortex-M processors this setting is enforced by
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* default and it is not configurable.
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*/
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#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
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SCB->CCR |= SCB_CCR_STKALIGN_Msk;
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#endif
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#endif /* CONFIG_STACK_ALIGN_DOUBLE_WORD */
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}
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_STACK_H_ */
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