118 lines
3.0 KiB
C
118 lines
3.0 KiB
C
/*
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* Copyright (c) 2018 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ARC_IOT_SOC_IRQ_H_
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#define _ARC_IOT_SOC_IRQ_H_
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#define IRQ_WATCHDOG 18
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#define IRQ_GPIO_4B0 19
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#define IRQ_DMA0_DONE 20
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#define IRQ_DMA1_DONE 21
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#define IRQ_DMA2_DONE 22
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#define IRQ_DMA3_DONE 23
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#define IRQ_DMA4_DONE 24
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#define IRQ_DMA5_DONE 25
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#define IRQ_DMA6_DONE 26
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#define IRQ_DMA7_DONE 27
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#define IRQ_DMA8_DONE 28
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#define IRQ_DMA9_DONE 29
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#define IRQ_DMA10_DONE 30
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#define IRQ_DMA11_DONE 31
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#define IRQ_DMA12_DONE 32
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#define IRQ_DMA13_DONE 33
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#define IRQ_DMA14_DONE 34
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#define IRQ_DMA15_DONE 35
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#define IRQ_DMA0_ERR 36
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#define IRQ_DMA1_ERR 37
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#define IRQ_DMA2_ERR 38
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#define IRQ_DMA3_ERR 39
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#define IRQ_DMA4_ERR 40
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#define IRQ_DMA5_ERR 41
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#define IRQ_DMA6_ERR 42
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#define IRQ_DMA7_ERR 43
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#define IRQ_DMA8_ERR 44
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#define IRQ_DMA9_ERR 45
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#define IRQ_DMA10_ERR 46
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#define IRQ_DMA11_ERR 47
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#define IRQ_DMA12_ERR 48
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#define IRQ_DMA13_ERR 49
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#define IRQ_DMA14_ERR 50
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#define IRQ_DMA15_ERR 51
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#define IRQ_GPIO_4B1 52
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#define IRQ_GPIO_4B2 53
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#define IRQ_GPIO_8B0 54
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#define IRQ_GPIO_8B1 55
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#define IRQ_GPIO_8B2 56
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#define IRQ_GPIO_8B3 57
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#define IRQ_I2CMST0_MST_ERR 58
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#define IRQ_I2CMST0_MST_RX_AVAIL 59
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#define IRQ_I2CMST0_MST_TX_REQ 60
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#define IRQ_I2CMST0_MST_STOP_DET 61
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#define IRQ_I2CMST1_MST_ERR 62
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#define IRQ_I2CMST1_MST_RX_AVAIL 63
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#define IRQ_I2CMST1_MST_TX_REQ 64
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#define IRQ_I2CMST1_MST_STOP_DET 65
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#define IRQ_I2CMST2_MST_ERR 66
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#define IRQ_I2CMST2_MST_RX_AVAIL 67
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#define IRQ_I2CMST2_MST_TX_REQ 68
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#define IRQ_I2CMST2_MST_STOP_DET 69
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/* SPI */
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#define IRQ_SPIMST0_MST_ERR 70
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#define IRQ_SPIMST0_MST_RX_AVAIL 71
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#define IRQ_SPIMST0_MST_TX_REQ 72
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#define IRQ_SPIMST0_MST_IDLE 73
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#define IRQ_SPIMST1_MST_ERR 74
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#define IRQ_SPIMST1_MST_RX_AVAIL 75
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#define IRQ_SPIMST1_MST_TX_REQ 76
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#define IRQ_SPIMST1_MST_IDLE 77
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#define IRQ_SPIMST2_MST_ERR 78
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#define IRQ_SPIMST2_MST_RX_AVAIL 79
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#define IRQ_SPIMST2_MST_TX_REQ 80
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#define IRQ_SPIMST2_MST_IDLE 81
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#define IRQ_SPISLV0_SLV_ERR 82
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#define IRQ_SPISLV0_SLV_RX_AVAIL 83
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#define IRQ_SPISLV0_SLV_TX_REQ 84
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#define IRQ_SPISLV0_SLV_IDLE 85
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/* UART */
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#define IRQ_UART0_UART 86
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#define IRQ_UART1_UART 87
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#define IRQ_UART2_UART 88
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#define IRQ_UART3_UART 89
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#define IRQ_EXT_WAKE_UP 90
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#define IRQ_SDIO 91
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/* I2S */
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#define IRQ_I2S_TX_EMP_0 92
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#define IRQ_I2S_TX_OR_0 93
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#define IRQ_I2S_RX_DA_0 94
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#define IRQ_I2S_RX_OR_0 95
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#define IRQ_USB 96
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#define IRQ_ADC 97
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#define IRQ_DW_TIMER0 98
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#define IRQ_DW_TIMER1 99
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#define IRQ_DW_TIMER2 100
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#define IRQ_DW_TIMER3 101
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#define IRQ_DW_TIMER4 102
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#define IRQ_DW_TIMER5 103
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#define IRQ_DW_RTC 104
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#define IRQ_DW_I3C 105
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#define IRQ_RESERVED0 106
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#define IRQ_RESERVED1 107
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#define IRQ_RESERVED2 108
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#define IRQ_RESERVED3 109
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#define IRQ_RESERVED4 110
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#endif /* _ARC_IOT_SOC_IRQ_H_ */
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