198 lines
7.3 KiB
C
198 lines
7.3 KiB
C
/*
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* Copyright (c) 2017 IpTronix S.r.l.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_SENSOR_ADXL362_ADXL362_H_
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#define ZEPHYR_DRIVERS_SENSOR_ADXL362_ADXL362_H_
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#include <zephyr/types.h>
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#include <device.h>
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#define ADXL362_SLAVE_ID 1
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/* ADXL362 communication commands */
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#define ADXL362_WRITE_REG 0x0A
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#define ADXL362_READ_REG 0x0B
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#define ADXL362_WRITE_FIFO 0x0D
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/* Registers */
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#define ADXL362_REG_DEVID_AD 0x00
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#define ADXL362_REG_DEVID_MST 0x01
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#define ADXL362_REG_PARTID 0x02
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#define ADXL362_REG_REVID 0x03
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#define ADXL362_REG_XDATA 0x08
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#define ADXL362_REG_YDATA 0x09
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#define ADXL362_REG_ZDATA 0x0A
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#define ADXL362_REG_STATUS 0x0B
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#define ADXL362_REG_FIFO_L 0x0C
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#define ADXL362_REG_FIFO_H 0x0D
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#define ADXL362_REG_XDATA_L 0x0E
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#define ADXL362_REG_XDATA_H 0x0F
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#define ADXL362_REG_YDATA_L 0x10
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#define ADXL362_REG_YDATA_H 0x11
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#define ADXL362_REG_ZDATA_L 0x12
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#define ADXL362_REG_ZDATA_H 0x13
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#define ADXL362_REG_TEMP_L 0x14
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#define ADXL362_REG_TEMP_H 0x15
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#define ADXL362_REG_SOFT_RESET 0x1F
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#define ADXL362_REG_THRESH_ACT_L 0x20
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#define ADXL362_REG_THRESH_ACT_H 0x21
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#define ADXL362_REG_TIME_ACT 0x22
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#define ADXL362_REG_THRESH_INACT_L 0x23
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#define ADXL362_REG_THRESH_INACT_H 0x24
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#define ADXL362_REG_TIME_INACT_L 0x25
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#define ADXL362_REG_TIME_INACT_H 0x26
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#define ADXL362_REG_ACT_INACT_CTL 0x27
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#define ADXL362_REG_FIFO_CTL 0x28
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#define ADXL362_REG_FIFO_SAMPLES 0x29
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#define ADXL362_REG_INTMAP1 0x2A
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#define ADXL362_REG_INTMAP2 0x2B
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#define ADXL362_REG_FILTER_CTL 0x2C
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#define ADXL362_REG_POWER_CTL 0x2D
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#define ADXL362_REG_SELF_TEST 0x2E
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/* ADXL362_REG_STATUS definitions */
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#define ADXL362_STATUS_ERR_USER_REGS (1 << 7)
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#define ADXL362_STATUS_AWAKE (1 << 6)
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#define ADXL362_STATUS_INACT (1 << 5)
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#define ADXL362_STATUS_ACT (1 << 4)
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#define ADXL362_STATUS_FIFO_OVERRUN (1 << 3)
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#define ADXL362_STATUS_FIFO_WATERMARK (1 << 2)
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#define ADXL362_STATUS_FIFO_RDY (1 << 1)
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#define ADXL362_STATUS_DATA_RDY (1 << 0)
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/* ADXL362_REG_ACT_INACT_CTL definitions */
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#define ADXL362_ACT_INACT_CTL_LINKLOOP(x) (((x) & 0x3) << 4)
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#define ADXL362_ACT_INACT_CTL_INACT_REF (1 << 3)
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#define ADXL362_ACT_INACT_CTL_INACT_EN (1 << 2)
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#define ADXL362_ACT_INACT_CTL_ACT_REF (1 << 1)
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#define ADXL362_ACT_INACT_CTL_ACT_EN (1 << 0)
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/* ADXL362_ACT_INACT_CTL_LINKLOOP(x) options */
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#define ADXL362_MODE_DEFAULT 0
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#define ADXL362_MODE_LINK 1
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#define ADXL362_MODE_LOOP 3
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/* ADXL362_REG_FIFO_CTL */
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#define ADXL362_FIFO_CTL_AH (1 << 3)
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#define ADXL362_FIFO_CTL_FIFO_TEMP (1 << 2)
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#define ADXL362_FIFO_CTL_FIFO_MODE(x) (((x) & 0x3) << 0)
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/* ADXL362_FIFO_CTL_FIFO_MODE(x) options */
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#define ADXL362_FIFO_DISABLE 0
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#define ADXL362_FIFO_OLDEST_SAVED 1
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#define ADXL362_FIFO_STREAM 2
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#define ADXL362_FIFO_TRIGGERED 3
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/* ADXL362_REG_INTMAP1 */
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#define ADXL362_INTMAP1_INT_LOW (1 << 7)
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#define ADXL362_INTMAP1_AWAKE (1 << 6)
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#define ADXL362_INTMAP1_INACT (1 << 5)
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#define ADXL362_INTMAP1_ACT (1 << 4)
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#define ADXL362_INTMAP1_FIFO_OVERRUN (1 << 3)
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#define ADXL362_INTMAP1_FIFO_WATERMARK (1 << 2)
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#define ADXL362_INTMAP1_FIFO_READY (1 << 1)
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#define ADXL362_INTMAP1_DATA_READY (1 << 0)
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/* ADXL362_REG_INTMAP2 definitions */
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#define ADXL362_INTMAP2_INT_LOW (1 << 7)
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#define ADXL362_INTMAP2_AWAKE (1 << 6)
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#define ADXL362_INTMAP2_INACT (1 << 5)
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#define ADXL362_INTMAP2_ACT (1 << 4)
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#define ADXL362_INTMAP2_FIFO_OVERRUN (1 << 3)
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#define ADXL362_INTMAP2_FIFO_WATERMARK (1 << 2)
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#define ADXL362_INTMAP2_FIFO_READY (1 << 1)
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#define ADXL362_INTMAP2_DATA_READY (1 << 0)
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/* ADXL362_REG_FILTER_CTL definitions */
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#define ADXL362_FILTER_CTL_RANGE(x) (((x) & 0x3) << 6)
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#define ADXL362_FILTER_CTL_RES (1 << 5)
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#define ADXL362_FILTER_CTL_HALF_BW (1 << 4)
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#define ADXL362_FILTER_CTL_EXT_SAMPLE (1 << 3)
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#define ADXL362_FILTER_CTL_ODR(x) (((x) & 0x7) << 0)
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/* ADXL362_FILTER_CTL_RANGE(x) options */
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#define ADXL362_RANGE_2G 0 /* +/-2 g */
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#define ADXL362_RANGE_4G 1 /* +/-4 g */
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#define ADXL362_RANGE_8G 2 /* +/-8 g */
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/* ADXL362_FILTER_CTL_ODR(x) options */
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#define ADXL362_ODR_12_5_HZ 0 /* 12.5 Hz */
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#define ADXL362_ODR_25_HZ 1 /* 25 Hz */
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#define ADXL362_ODR_50_HZ 2 /* 50 Hz */
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#define ADXL362_ODR_100_HZ 3 /* 100 Hz */
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#define ADXL362_ODR_200_HZ 4 /* 200 Hz */
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#define ADXL362_ODR_400_HZ 5 /* 400 Hz */
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/* ADXL362_REG_POWER_CTL definitions */
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#define ADXL362_POWER_CTL_RES (1 << 7)
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#define ADXL362_POWER_CTL_EXT_CLK (1 << 6)
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#define ADXL362_POWER_CTL_LOW_NOISE(x) (((x) & 0x3) << 4)
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#define ADXL362_POWER_CTL_WAKEUP (1 << 3)
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#define ADXL362_POWER_CTL_AUTOSLEEP (1 << 2)
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#define ADXL362_POWER_CTL_MEASURE(x) (((x) & 0x3) << 0)
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/* ADXL362_POWER_CTL_LOW_NOISE(x) options */
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#define ADXL362_NOISE_MODE_NORMAL 0
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#define ADXL362_NOISE_MODE_LOW 1
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#define ADXL362_NOISE_MODE_ULTRALOW 2
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/* ADXL362_POWER_CTL_MEASURE(x) options */
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#define ADXL362_MEASURE_STANDBY 0
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#define ADXL362_MEASURE_ON 2
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/* ADXL362_REG_SELF_TEST */
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#define ADXL362_SELF_TEST_ST (1 << 0)
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/* ADXL362 device information */
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#define ADXL362_DEVICE_AD 0xAD
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#define ADXL362_DEVICE_MST 0x1D
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#define ADXL362_PART_ID 0xF2
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/* ADXL362 Reset settings */
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#define ADXL362_RESET_KEY 0x52
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struct adxl362_config {
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char *spi_name;
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u32_t spi_max_frequency;
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u16_t spi_slave;
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};
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struct adxl362_data {
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struct device *spi;
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struct spi_config spi_cfg;
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s32_t acc_x;
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s32_t acc_y;
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s32_t acc_z;
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s32_t temp;
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u8_t selected_range;
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};
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#if defined(CONFIG_ADXL362_ACCEL_RANGE_RUNTIME) ||\
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defined(CONFIG_ADXL362_ACCEL_RANGE_2G)
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# define ADXL362_DEFAULT_RANGE_ACC ADXL362_RANGE_2G
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#elif defined(CONFIG_ADXL362_ACCEL_RANGE_4G)
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# define ADXL362_DEFAULT_RANGE_ACC ADXL362_RANGE_4G
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#else
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# define ADXL362_DEFAULT_RANGE_ACC ADXL362_RANGE_8G
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#endif
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#if defined(CONFIG_ADXL362_ACCEL_ODR_RUNTIME) ||\
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defined(CONFIG_ADXL362_ACCEL_ODR_12_5)
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# define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_12_5_HZ
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#elif defined(CONFIG_ADXL362_ACCEL_ODR_25)
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# define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_25_HZ
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#elif defined(CONFIG_ADXL362_ACCEL_ODR_50)
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# define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_50_HZ
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#elif defined(CONFIG_ADXL362_ACCEL_ODR_100)
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# define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_100_HZ
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#elif defined(CONFIG_ADXL362_ACCEL_ODR_200)
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# define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_200_HZ
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#else
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# define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_400_HZ
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#endif
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#endif /* ZEPHYR_DRIVERS_SENSOR_ADXL362_ADXL362_H_ */
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