48 lines
1.3 KiB
Plaintext
48 lines
1.3 KiB
Plaintext
/*
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* Copyright (c) 2021 Nordic Semiconductor ASA
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* Copyright (c) 2024 Embeint Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* This file specifies the default shared memory region used for inter-procesor
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* communication between the application and network cores.
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*
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* This file, or a board specific variant of it, must be included by both
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* cpuapp and cpunet application to ensure both processors have the same
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* expectations of the memory region used. If a board specific variant is
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* used, it is up to the author to ensure the shared memory region resides in
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* the memory range allocated to the non-secure image (sram0_ns).
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*
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* By default the last 64 kB of application core SRAM is allocated as shared
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* memory (sram0_shared) which is divided in:
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* - 32 kB CPUAPP to CPUNET communication (cpuapp_cpunet_ipc_shm)
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* - 32 kB CPUNET to CPUAPP communication (cpunet_cpuapp_ipc_shm)
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*/
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/ {
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chosen {
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zephyr,ipc_shm = &sram0_shared;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram0_shared: memory@20070000 {
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#address-cells = <1>;
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#size-cells = <1>;
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/* Last 64 kB of sram0 */
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reg = <0x20070000 0x10000>;
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cpuapp_cpunet_ipc_shm: memory@20070000 {
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reg = <0x20070000 DT_SIZE_K(32)>;
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};
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cpunet_cpuapp_ipc_shm: memory@20078000 {
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reg = <0x20078000 DT_SIZE_K(32)>;
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};
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};
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};
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};
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