307 lines
6.9 KiB
C
307 lines
6.9 KiB
C
/*
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* Copyright (c) 2018 Marvell
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* Copyright (c) 2018 Lexmark International, Inc.
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* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* NOTE: This driver implements the GICv1 and GICv2 interfaces.
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*/
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#include <zephyr/device.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/sw_isr_table.h>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <zephyr/drivers/interrupt_controller/gic.h>
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#include <zephyr/sys/barrier.h>
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#if defined(CONFIG_GIC_V1)
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#define DT_DRV_COMPAT arm_gic_v1
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#elif defined(CONFIG_GIC_V2)
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#define DT_DRV_COMPAT arm_gic_v2
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#else
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#error "Unknown GIC controller compatible for this configuration"
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#endif
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static const uint64_t cpu_mpid_list[] = {
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DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(cpus), DT_REG_ADDR, (,))
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};
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BUILD_ASSERT(ARRAY_SIZE(cpu_mpid_list) >= CONFIG_MP_MAX_NUM_CPUS,
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"The count of CPU Cores nodes in dts is less than CONFIG_MP_MAX_NUM_CPUS\n");
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void arm_gic_irq_enable(unsigned int irq)
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{
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int int_grp, int_off;
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int_grp = irq / 32;
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int_off = irq % 32;
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sys_write32((1 << int_off), (GICD_ISENABLERn + int_grp * 4));
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}
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void arm_gic_irq_disable(unsigned int irq)
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{
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int int_grp, int_off;
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int_grp = irq / 32;
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int_off = irq % 32;
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sys_write32((1 << int_off), (GICD_ICENABLERn + int_grp * 4));
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}
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bool arm_gic_irq_is_enabled(unsigned int irq)
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{
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int int_grp, int_off;
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unsigned int enabler;
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int_grp = irq / 32;
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int_off = irq % 32;
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enabler = sys_read32(GICD_ISENABLERn + int_grp * 4);
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return (enabler & (1 << int_off)) != 0;
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}
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bool arm_gic_irq_is_pending(unsigned int irq)
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{
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int int_grp, int_off;
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unsigned int enabler;
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int_grp = irq / 32;
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int_off = irq % 32;
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enabler = sys_read32(GICD_ISPENDRn + int_grp * 4);
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return (enabler & (1 << int_off)) != 0;
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}
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void arm_gic_irq_set_pending(unsigned int irq)
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{
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int int_grp, int_off;
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int_grp = irq / 32;
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int_off = irq % 32;
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sys_write32((1 << int_off), (GICD_ISPENDRn + int_grp * 4));
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}
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void arm_gic_irq_clear_pending(unsigned int irq)
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{
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int int_grp, int_off;
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int_grp = irq / 32;
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int_off = irq % 32;
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sys_write32((1 << int_off), (GICD_ICPENDRn + int_grp * 4));
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}
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void arm_gic_irq_set_priority(
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unsigned int irq, unsigned int prio, uint32_t flags)
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{
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int int_grp, int_off;
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uint32_t val;
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/* Set priority */
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sys_write8(prio & 0xff, GICD_IPRIORITYRn + irq);
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/* Set interrupt type */
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int_grp = (irq / 16) * 4;
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int_off = (irq % 16) * 2;
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val = sys_read32(GICD_ICFGRn + int_grp);
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val &= ~(GICD_ICFGR_MASK << int_off);
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if (flags & IRQ_TYPE_EDGE) {
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val |= (GICD_ICFGR_TYPE << int_off);
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}
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sys_write32(val, GICD_ICFGRn + int_grp);
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}
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unsigned int arm_gic_get_active(void)
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{
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unsigned int irq;
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/*
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* "ARM Generic Interrupt Controller Architecture version 2.0" states that
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* [4.4.5 End of Interrupt Register, GICC_EOIR)]:
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* """
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* For compatibility with possible extensions to the GIC architecture
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* specification, ARM recommends that software preserves the entire register
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* value read from the GICC_IAR when it acknowledges the interrupt, and uses
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* that entire value for its corresponding write to the GICC_EOIR.
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* """
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* Because of that, we read the entire value here, to be later written back to GICC_EOIR
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*/
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irq = sys_read32(GICC_IAR);
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return irq;
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}
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void arm_gic_eoi(unsigned int irq)
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{
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/*
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* Ensure the write to peripheral registers are *complete* before the write
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* to GIC_EOIR.
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*
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* Note: The completion guarantee depends on various factors of system design
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* and the barrier is the best core can do by which execution of further
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* instructions waits till the barrier is alive.
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*/
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barrier_dsync_fence_full();
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/* set to inactive */
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sys_write32(irq, GICC_EOIR);
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}
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void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
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uint16_t target_list)
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{
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uint32_t sgi_val;
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ARG_UNUSED(target_aff);
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sgi_val = GICD_SGIR_TGTFILT_CPULIST |
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GICD_SGIR_CPULIST(target_list & GICD_SGIR_CPULIST_MASK) |
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sgi_id;
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barrier_dsync_fence_full();
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sys_write32(sgi_val, GICD_SGIR);
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barrier_isync_fence_full();
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}
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static void gic_dist_init(void)
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{
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unsigned int gic_irqs, i;
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uint8_t cpu_mask = 0;
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uint32_t reg_val;
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gic_irqs = sys_read32(GICD_TYPER) & 0x1f;
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gic_irqs = (gic_irqs + 1) * 32;
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if (gic_irqs > 1020) {
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gic_irqs = 1020;
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}
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/*
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* Disable the forwarding of pending interrupts
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* from the Distributor to the CPU interfaces
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*/
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sys_write32(0, GICD_CTLR);
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/*
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* Enable all global interrupts distributing to CPUs listed
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* in dts with the count of arch_num_cpus().
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*/
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unsigned int num_cpus = arch_num_cpus();
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for (i = 0; i < num_cpus; i++) {
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cpu_mask |= BIT(cpu_mpid_list[i]);
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}
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reg_val = cpu_mask | (cpu_mask << 8) | (cpu_mask << 16)
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| (cpu_mask << 24);
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for (i = GIC_SPI_INT_BASE; i < gic_irqs; i += 4) {
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sys_write32(reg_val, GICD_ITARGETSRn + i);
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}
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/*
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* Set all global interrupts to be level triggered, active low.
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*/
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for (i = GIC_SPI_INT_BASE; i < gic_irqs; i += 16) {
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sys_write32(0, GICD_ICFGRn + i / 4);
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}
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/* Set priority on all global interrupts. */
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for (i = GIC_SPI_INT_BASE; i < gic_irqs; i += 4) {
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sys_write32(0, GICD_IPRIORITYRn + i);
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}
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/* Set all interrupts to group 0 */
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for (i = GIC_SPI_INT_BASE; i < gic_irqs; i += 32) {
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sys_write32(0, GICD_IGROUPRn + i / 8);
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}
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/*
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* Disable all interrupts. Leave the PPI and SGIs alone
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* as these enables are banked registers.
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*/
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for (i = GIC_SPI_INT_BASE; i < gic_irqs; i += 32) {
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#ifndef CONFIG_GIC_V1
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sys_write32(0xffffffff, GICD_ICACTIVERn + i / 8);
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#endif
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sys_write32(0xffffffff, GICD_ICENABLERn + i / 8);
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}
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/*
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* Enable the forwarding of pending interrupts
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* from the Distributor to the CPU interfaces
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*/
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sys_write32(1, GICD_CTLR);
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}
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static void gic_cpu_init(void)
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{
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int i;
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uint32_t val;
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/*
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* Deal with the banked PPI and SGI interrupts - disable all
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* PPI interrupts, ensure all SGI interrupts are enabled.
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*/
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#ifndef CONFIG_GIC_V1
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sys_write32(0xffffffff, GICD_ICACTIVERn);
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#endif
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sys_write32(0xffff0000, GICD_ICENABLERn);
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sys_write32(0x0000ffff, GICD_ISENABLERn);
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/*
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* Set priority on PPI and SGI interrupts
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*/
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for (i = 0; i < 32; i += 4) {
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sys_write32(0xa0a0a0a0, GICD_IPRIORITYRn + i);
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}
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sys_write32(0xf0, GICC_PMR);
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/*
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* Enable interrupts and signal them using the IRQ signal.
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*/
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val = sys_read32(GICC_CTLR);
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#ifndef CONFIG_GIC_V1
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val &= ~GICC_CTLR_BYPASS_MASK;
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#endif
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val |= GICC_CTLR_ENABLE_MASK;
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sys_write32(val, GICC_CTLR);
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}
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#define GIC_PARENT_IRQ 0
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#define GIC_PARENT_IRQ_PRI 0
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#define GIC_PARENT_IRQ_FLAGS 0
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/**
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* @brief Initialize the GIC device driver
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*/
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int arm_gic_init(const struct device *dev)
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{
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/* Init of Distributor interface registers */
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gic_dist_init();
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/* Init CPU interface registers */
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gic_cpu_init();
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return 0;
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}
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DEVICE_DT_INST_DEFINE(0, arm_gic_init, NULL, NULL, NULL,
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PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
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#ifdef CONFIG_SMP
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void arm_gic_secondary_init(void)
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{
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/* Init CPU interface registers for each secondary core */
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gic_cpu_init();
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}
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#endif
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