230 lines
6.8 KiB
C
230 lines
6.8 KiB
C
/*
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* Copyright (c) 2023 Nordic Semiconductor ASA
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nordic_npm1300_gpio
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#include <errno.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/drivers/mfd/npm1300.h>
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#include <zephyr/dt-bindings/gpio/nordic-npm1300-gpio.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/util_macro.h>
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/* nPM1300 GPIO base address */
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#define NPM_GPIO_BASE 0x06U
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/* nPM1300 GPIO registers offsets */
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#define NPM_GPIO_OFFSET_MODE 0x00U
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#define NPM_GPIO_OFFSET_DRIVE 0x05U
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#define NPM_GPIO_OFFSET_PULLUP 0x0AU
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#define NPM_GPIO_OFFSET_PULLDOWN 0x0FU
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#define NPM_GPIO_OFFSET_OPENDRAIN 0x14U
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#define NPM_GPIO_OFFSET_DEBOUNCE 0x19U
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#define NPM_GPIO_OFFSET_STATUS 0x1EU
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/* nPM1300 Channel counts */
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#define NPM1300_GPIO_PINS 5U
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#define NPM1300_GPIO_GPIINPUT 0
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#define NPM1300_GPIO_GPILOGIC1 1
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#define NPM1300_GPIO_GPILOGIC0 2
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#define NPM1300_GPIO_GPIEVENTRISE 3
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#define NPM1300_GPIO_GPIEVENTFALL 4
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#define NPM1300_GPIO_GPOIRQ 5
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#define NPM1300_GPIO_GPORESET 6
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#define NPM1300_GPIO_GPOPWRLOSSWARN 7
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#define NPM1300_GPIO_GPOLOGIC1 8
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#define NPM1300_GPIO_GPOLOGIC0 9
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struct gpio_npm1300_config {
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struct gpio_driver_config common;
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const struct device *mfd;
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};
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struct gpio_npm1300_data {
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struct gpio_driver_data common;
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};
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static int gpio_npm1300_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_npm1300_config *config = dev->config;
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int ret;
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uint8_t data;
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ret = mfd_npm1300_reg_read(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_STATUS, &data);
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if (ret < 0) {
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return ret;
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}
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*value = data;
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return 0;
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}
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static int gpio_npm1300_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_npm1300_config *config = dev->config;
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int ret = 0;
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for (size_t idx = 0; idx < NPM1300_GPIO_PINS; idx++) {
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if ((mask & BIT(idx)) != 0U) {
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if ((value & BIT(idx)) != 0U) {
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ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE,
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NPM_GPIO_OFFSET_MODE + idx,
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NPM1300_GPIO_GPOLOGIC1);
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} else {
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ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE,
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NPM_GPIO_OFFSET_MODE + idx,
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NPM1300_GPIO_GPOLOGIC0);
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}
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if (ret != 0U) {
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return ret;
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}
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}
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}
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return ret;
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}
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static int gpio_npm1300_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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return gpio_npm1300_port_set_masked_raw(dev, pins, pins);
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}
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static int gpio_npm1300_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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return gpio_npm1300_port_set_masked_raw(dev, pins, 0U);
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}
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static inline int gpio_npm1300_configure(const struct device *dev, gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_npm1300_config *config = dev->config;
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int ret = 0;
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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if (pin >= NPM1300_GPIO_PINS) {
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return -EINVAL;
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}
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/* Configure mode */
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if ((flags & GPIO_INPUT) != 0U) {
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if (flags & GPIO_ACTIVE_LOW) {
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ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE,
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NPM_GPIO_OFFSET_MODE + pin,
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NPM1300_GPIO_GPIEVENTFALL);
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} else {
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ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE,
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NPM_GPIO_OFFSET_MODE + pin,
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NPM1300_GPIO_GPIEVENTRISE);
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}
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} else if ((flags & NPM1300_GPIO_WDT_RESET_ON) != 0U) {
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ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_MODE + pin,
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NPM1300_GPIO_GPORESET);
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} else if ((flags & NPM1300_GPIO_PWRLOSSWARN_ON) != 0U) {
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ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_MODE + pin,
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NPM1300_GPIO_GPOPWRLOSSWARN);
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} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
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ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_MODE + pin,
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NPM1300_GPIO_GPOLOGIC1);
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} else if ((flags & GPIO_OUTPUT) != 0U) {
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ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_MODE + pin,
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NPM1300_GPIO_GPOLOGIC0);
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}
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if (ret < 0) {
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return ret;
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}
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/* Configure open drain */
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ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_OPENDRAIN + pin,
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!!(flags & GPIO_SINGLE_ENDED));
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if (ret < 0) {
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return ret;
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}
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/* Configure pulls */
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ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_PULLUP + pin,
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!!(flags & GPIO_PULL_UP));
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if (ret < 0) {
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return ret;
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}
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ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_PULLDOWN + pin,
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!!(flags & GPIO_PULL_DOWN));
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if (ret < 0) {
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return ret;
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}
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/* Configure drive strength and debounce */
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ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_DRIVE + pin,
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!!(flags & NPM1300_GPIO_DRIVE_6MA));
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if (ret < 0) {
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return ret;
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}
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ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_DEBOUNCE + pin,
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!!(flags & NPM1300_GPIO_DEBOUNCE_ON));
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return ret;
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}
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static int gpio_npm1300_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
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{
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int ret;
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uint32_t value;
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ret = gpio_npm1300_port_get_raw(dev, &value);
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if (ret < 0) {
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return ret;
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}
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return gpio_npm1300_port_set_masked_raw(dev, pins, ~value);
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}
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static const struct gpio_driver_api gpio_npm1300_api = {
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.pin_configure = gpio_npm1300_configure,
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.port_get_raw = gpio_npm1300_port_get_raw,
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.port_set_masked_raw = gpio_npm1300_port_set_masked_raw,
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.port_set_bits_raw = gpio_npm1300_port_set_bits_raw,
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.port_clear_bits_raw = gpio_npm1300_port_clear_bits_raw,
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.port_toggle_bits = gpio_npm1300_port_toggle_bits,
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};
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static int gpio_npm1300_init(const struct device *dev)
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{
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const struct gpio_npm1300_config *config = dev->config;
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if (!device_is_ready(config->mfd)) {
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return -ENODEV;
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}
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return 0;
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}
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#define GPIO_NPM1300_DEFINE(n) \
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static const struct gpio_npm1300_config gpio_npm1300_config##n = { \
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.common = \
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{ \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.mfd = DEVICE_DT_GET(DT_INST_PARENT(n))}; \
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\
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static struct gpio_npm1300_data gpio_npm1300_data##n; \
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\
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DEVICE_DT_INST_DEFINE(n, gpio_npm1300_init, NULL, &gpio_npm1300_data##n, \
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&gpio_npm1300_config##n, POST_KERNEL, \
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CONFIG_GPIO_NPM1300_INIT_PRIORITY, &gpio_npm1300_api);
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DT_INST_FOREACH_STATUS_OKAY(GPIO_NPM1300_DEFINE)
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