409 lines
11 KiB
C
409 lines
11 KiB
C
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_gpio
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/irq.h>
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#include <soc.h>
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#include <fsl_common.h>
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#include <fsl_gpio.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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struct mcux_igpio_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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GPIO_Type *base;
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const struct pinctrl_soc_pinmux *pin_muxes;
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uint8_t mux_count;
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};
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struct mcux_igpio_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data general;
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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};
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static int mcux_igpio_configure(const struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct mcux_igpio_config *config = dev->config;
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GPIO_Type *base = config->base;
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struct pinctrl_soc_pin pin_cfg;
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int cfg_idx = pin, i;
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/* Make sure pin is supported */
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if ((config->common.port_pin_mask & BIT(pin)) == 0) {
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return -ENOTSUP;
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}
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/* Some SOCs have non-contiguous gpio pin layouts, account for this */
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for (i = 0; i < pin; i++) {
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if ((config->common.port_pin_mask & BIT(i)) == 0) {
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cfg_idx--;
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}
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}
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/* Init pin configuration struct, and use pinctrl api to apply settings */
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if (cfg_idx >= config->mux_count) {
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/* Pin is not connected to a mux */
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return -ENOTSUP;
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}
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/* Set appropriate bits in pin configuration register */
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volatile uint32_t *gpio_cfg_reg =
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(volatile uint32_t *)config->pin_muxes[cfg_idx].config_register;
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uint32_t reg = *gpio_cfg_reg;
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#ifdef CONFIG_SOC_SERIES_IMXRT10XX
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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/* Set ODE bit */
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reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
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} else {
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reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
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}
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if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
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reg |= IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
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if (((flags & GPIO_PULL_UP) != 0)) {
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/* Use 100K pullup */
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reg |= IOMUXC_SW_PAD_CTL_PAD_PUS(2);
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} else {
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/* 100K pulldown */
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reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
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}
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} else {
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/* Set pin to keeper */
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reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
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}
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#elif defined(CONFIG_SOC_SERIES_IMXRT11XX)
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if (config->pin_muxes[pin].pue_mux) {
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/* PUE type register layout (GPIO_AD pins) */
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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/* Set ODE bit */
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reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
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} else {
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reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
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}
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if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
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reg |= IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
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if (((flags & GPIO_PULL_UP) != 0)) {
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reg |= IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
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} else {
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reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
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}
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} else {
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/* Set pin to highz */
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reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
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}
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} else {
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/* PDRV/SNVS/LPSR type register layout */
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if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
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reg &= ~IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
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if (((flags & GPIO_PULL_UP) != 0)) {
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reg |= IOMUXC_SW_PAD_CTL_PAD_PULL(0x1U);
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} else {
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reg |= IOMUXC_SW_PAD_CTL_PAD_PULL(0x2U);
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}
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} else {
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/* Set pin to no pull */
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reg |= IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
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}
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/* PDRV/SNVS/LPSR reg have different ODE bits */
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if (config->pin_muxes[cfg_idx].pdrv_mux) {
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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/* Set ODE bit */
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reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
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} else {
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reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
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}
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} else if (config->pin_muxes[cfg_idx].lpsr_mux) {
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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/* Set ODE bit */
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reg |= (IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 1);
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} else {
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reg &= ~(IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 1);
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}
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} else if (config->pin_muxes[cfg_idx].snvs_mux) {
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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/* Set ODE bit */
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reg |= (IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 2);
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} else {
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reg &= ~(IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 2);
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}
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}
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}
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#elif defined(CONFIG_SOC_MIMX8MQ6_M4)
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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/* Set ODE bit */
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reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
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} else {
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reg &= ~(0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
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}
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if ((flags & GPIO_PULL_UP) != 0) {
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reg |= (0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
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}
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if ((flag & GPIO_PULL_DOWN) != 0) {
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return -ENOTSUP;
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}
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#else
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/* Default flags, should work for most SOCs */
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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/* Set ODE bit */
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reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
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} else {
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reg &= ~(0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
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}
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if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
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reg |= (0x1 << MCUX_IMX_BIAS_PULL_ENABLE_SHIFT);
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if (((flags & GPIO_PULL_UP) != 0)) {
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reg |= (0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
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} else {
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reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
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}
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} else {
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/* Set pin to highz */
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reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_ENABLE_SHIFT);
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}
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#endif /* CONFIG_SOC_SERIES_IMXRT10XX */
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memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg.pinmux));
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/* cfg register will be set by pinctrl_configure_pins */
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pin_cfg.pin_ctrl_flags = reg;
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pinctrl_configure_pins(&pin_cfg, 1, PINCTRL_REG_NONE);
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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GPIO_WritePinOutput(base, pin, 1);
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}
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if (flags & GPIO_OUTPUT_INIT_LOW) {
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GPIO_WritePinOutput(base, pin, 0);
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}
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WRITE_BIT(base->GDIR, pin, flags & GPIO_OUTPUT);
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return 0;
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}
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static int mcux_igpio_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct mcux_igpio_config *config = dev->config;
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GPIO_Type *base = config->base;
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*value = base->DR;
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return 0;
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}
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static int mcux_igpio_port_set_masked_raw(const struct device *dev,
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uint32_t mask,
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uint32_t value)
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{
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const struct mcux_igpio_config *config = dev->config;
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GPIO_Type *base = config->base;
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base->DR = (base->DR & ~mask) | (mask & value);
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return 0;
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}
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static int mcux_igpio_port_set_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct mcux_igpio_config *config = dev->config;
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GPIO_Type *base = config->base;
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GPIO_PortSet(base, mask);
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return 0;
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}
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static int mcux_igpio_port_clear_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct mcux_igpio_config *config = dev->config;
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GPIO_Type *base = config->base;
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GPIO_PortClear(base, mask);
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return 0;
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}
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static int mcux_igpio_port_toggle_bits(const struct device *dev,
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uint32_t mask)
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{
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const struct mcux_igpio_config *config = dev->config;
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GPIO_Type *base = config->base;
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GPIO_PortToggle(base, mask);
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return 0;
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}
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static int mcux_igpio_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct mcux_igpio_config *config = dev->config;
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GPIO_Type *base = config->base;
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unsigned int key;
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uint8_t icr;
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int shift;
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/* Make sure pin is supported */
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if ((config->common.port_pin_mask & BIT(pin)) == 0) {
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return -ENOTSUP;
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}
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if (mode == GPIO_INT_MODE_DISABLED) {
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key = irq_lock();
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WRITE_BIT(base->IMR, pin, 0);
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irq_unlock(key);
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return 0;
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}
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if ((mode == GPIO_INT_MODE_EDGE) && (trig == GPIO_INT_TRIG_LOW)) {
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icr = 3;
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} else if ((mode == GPIO_INT_MODE_EDGE) &&
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(trig == GPIO_INT_TRIG_HIGH)) {
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icr = 2;
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} else if ((mode == GPIO_INT_MODE_LEVEL) &&
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(trig == GPIO_INT_TRIG_HIGH)) {
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icr = 1;
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} else {
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icr = 0;
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}
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if (pin < 16) {
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shift = 2 * pin;
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base->ICR1 = (base->ICR1 & ~(3 << shift)) | (icr << shift);
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} else if (pin < 32) {
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shift = 2 * (pin - 16);
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base->ICR2 = (base->ICR2 & ~(3 << shift)) | (icr << shift);
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} else {
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return -EINVAL;
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}
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key = irq_lock();
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WRITE_BIT(base->EDGE_SEL, pin, trig == GPIO_INT_TRIG_BOTH);
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WRITE_BIT(base->ISR, pin, 1);
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WRITE_BIT(base->IMR, pin, 1);
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irq_unlock(key);
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return 0;
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}
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static int mcux_igpio_manage_callback(const struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct mcux_igpio_data *data = dev->data;
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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static void mcux_igpio_port_isr(const struct device *dev)
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{
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const struct mcux_igpio_config *config = dev->config;
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struct mcux_igpio_data *data = dev->data;
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GPIO_Type *base = config->base;
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uint32_t int_flags;
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int_flags = base->ISR;
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base->ISR = int_flags;
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gpio_fire_callbacks(&data->callbacks, dev, int_flags);
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}
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static const struct gpio_driver_api mcux_igpio_driver_api = {
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.pin_configure = mcux_igpio_configure,
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.port_get_raw = mcux_igpio_port_get_raw,
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.port_set_masked_raw = mcux_igpio_port_set_masked_raw,
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.port_set_bits_raw = mcux_igpio_port_set_bits_raw,
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.port_clear_bits_raw = mcux_igpio_port_clear_bits_raw,
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.port_toggle_bits = mcux_igpio_port_toggle_bits,
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.pin_interrupt_configure = mcux_igpio_pin_interrupt_configure,
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.manage_callback = mcux_igpio_manage_callback,
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};
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/* These macros will declare an array of pinctrl_soc_pinmux types */
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#define PINMUX_INIT(node, prop, idx) MCUX_IMX_PINMUX(DT_PROP_BY_IDX(node, prop, idx)),
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#define MCUX_IGPIO_PIN_DECLARE(n) \
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const struct pinctrl_soc_pinmux mcux_igpio_pinmux_##n[] = { \
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DT_FOREACH_PROP_ELEM(DT_DRV_INST(n), pinmux, PINMUX_INIT) \
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};
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#define MCUX_IGPIO_PIN_INIT(n) \
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.pin_muxes = mcux_igpio_pinmux_##n, \
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.mux_count = DT_PROP_LEN(DT_DRV_INST(n), pinmux)
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#define MCUX_IGPIO_IRQ_INIT(n, i) \
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do { \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, i, irq), \
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DT_INST_IRQ_BY_IDX(n, i, priority), \
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mcux_igpio_port_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQ_BY_IDX(n, i, irq)); \
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} while (false)
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#define MCUX_IGPIO_INIT(n) \
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MCUX_IGPIO_PIN_DECLARE(n) \
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static int mcux_igpio_##n##_init(const struct device *dev); \
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\
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static const struct mcux_igpio_config mcux_igpio_##n##_config = {\
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.common = { \
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.port_pin_mask = GPIO_DT_INST_PORT_PIN_MASK_NGPIOS_EXC(\
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n, DT_INST_PROP(n, ngpios)),\
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}, \
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.base = (GPIO_Type *)DT_INST_REG_ADDR(n), \
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MCUX_IGPIO_PIN_INIT(n) \
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}; \
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\
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static struct mcux_igpio_data mcux_igpio_##n##_data; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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mcux_igpio_##n##_init, \
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NULL, \
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&mcux_igpio_##n##_data, \
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&mcux_igpio_##n##_config, \
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POST_KERNEL, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&mcux_igpio_driver_api); \
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\
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static int mcux_igpio_##n##_init(const struct device *dev) \
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{ \
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IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \
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(MCUX_IGPIO_IRQ_INIT(n, 0);)) \
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\
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IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 1), \
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(MCUX_IGPIO_IRQ_INIT(n, 1);)) \
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\
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return 0; \
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}
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DT_INST_FOREACH_STATUS_OKAY(MCUX_IGPIO_INIT)
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