356 lines
11 KiB
C
356 lines
11 KiB
C
/*
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* Copyright (c) 2023 Chen Xingyu <hi@xingrz.me>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT brcm_bcm2711_gpio
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/irq.h>
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#define GPIO_REG_GROUP(n, cnt) (n / cnt)
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#define GPIO_REG_SHIFT(n, cnt, bits) ((n % cnt) * bits)
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#define GPFSEL(base, n) (base + 0x00 + 0x04 * n)
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#define GPSET(base, n) (base + 0x1C + 0x04 * n)
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#define GPCLR(base, n) (base + 0x28 + 0x04 * n)
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#define GPLEV(base, n) (base + 0x34 + 0x04 * n)
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#define GPEDS(base, n) (base + 0x40 + 0x04 * n)
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#define GPREN(base, n) (base + 0x4C + 0x04 * n)
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#define GPFEN(base, n) (base + 0x58 + 0x04 * n)
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#define GPHEN(base, n) (base + 0x64 + 0x04 * n)
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#define GPLEN(base, n) (base + 0x70 + 0x04 * n)
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#define GPAREN(base, n) (base + 0x7C + 0x04 * n)
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#define GPAFEN(base, n) (base + 0x88 + 0x04 * n)
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#define GPPULL(base, n) (base + 0xE4 + 0x04 * n)
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#define FSEL_GROUPS (10)
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#define FSEL_BITS (3)
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#define FSEL_OUTPUT (0x1)
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#define IO_GROUPS (32)
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#define IO_BITS (1)
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#define PULL_GROUPS (16)
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#define PULL_BITS (2)
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#define PULL_UP (0x1)
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#define PULL_DOWN (0x2)
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#define DEV_CFG(dev) ((const struct gpio_bcm2711_config *const)(dev)->config)
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#define DEV_DATA(dev) ((struct gpio_bcm2711_data *const)(dev)->data)
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#define RPI_PIN_NUM(dev, n) (DEV_CFG(dev)->offset + n)
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#define FROM_U64(val, idx) ((uint32_t)((val >> (idx * 32)) & UINT32_MAX))
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struct gpio_bcm2711_config {
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struct gpio_driver_config common;
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DEVICE_MMIO_NAMED_ROM(reg_base);
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void (*irq_config_func)(void);
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uint8_t offset;
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uint8_t ngpios;
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};
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struct gpio_bcm2711_data {
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struct gpio_driver_data common;
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DEVICE_MMIO_NAMED_RAM(reg_base);
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mem_addr_t base;
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sys_slist_t cb;
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};
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static int gpio_bcm2711_pin_configure(const struct device *port, gpio_pin_t pin, gpio_flags_t flags)
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{
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struct gpio_bcm2711_data *data = DEV_DATA(port);
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uint32_t group;
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uint32_t shift;
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uint32_t regval;
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if (flags & GPIO_OPEN_DRAIN) {
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return -ENOTSUP;
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}
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/* Set direction */
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{
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group = GPIO_REG_GROUP(RPI_PIN_NUM(port, pin), FSEL_GROUPS);
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shift = GPIO_REG_SHIFT(RPI_PIN_NUM(port, pin), FSEL_GROUPS, FSEL_BITS);
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regval = sys_read32(GPFSEL(data->base, group));
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regval &= ~(BIT_MASK(FSEL_BITS) << shift);
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if (flags & GPIO_OUTPUT) {
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regval |= (FSEL_OUTPUT << shift);
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}
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sys_write32(regval, GPFSEL(data->base, group));
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}
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/* Set output level */
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if (flags & GPIO_OUTPUT) {
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group = GPIO_REG_GROUP(RPI_PIN_NUM(port, pin), IO_GROUPS);
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shift = GPIO_REG_SHIFT(RPI_PIN_NUM(port, pin), IO_GROUPS, IO_BITS);
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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regval = sys_read32(GPSET(data->base, group));
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regval |= BIT(shift);
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sys_write32(regval, GPSET(data->base, group));
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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regval = sys_read32(GPCLR(data->base, group));
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regval |= BIT(shift);
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sys_write32(regval, GPCLR(data->base, group));
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}
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}
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/* Set pull */
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{
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group = GPIO_REG_GROUP(RPI_PIN_NUM(port, pin), PULL_GROUPS);
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shift = GPIO_REG_SHIFT(RPI_PIN_NUM(port, pin), PULL_GROUPS, PULL_BITS);
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regval = sys_read32(GPPULL(data->base, group));
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regval &= ~(BIT_MASK(PULL_BITS) << shift);
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if (flags & GPIO_PULL_UP) {
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regval |= (PULL_UP << shift);
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} else if (flags & GPIO_PULL_DOWN) {
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regval |= (PULL_DOWN << shift);
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}
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sys_write32(regval, GPPULL(data->base, group));
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}
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return 0;
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}
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static int gpio_bcm2711_port_get_raw(const struct device *port, gpio_port_value_t *value)
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{
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const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
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struct gpio_bcm2711_data *data = DEV_DATA(port);
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uint64_t regval;
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regval = ((uint64_t)sys_read32(GPLEV(data->base, 0))) |
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((uint64_t)sys_read32(GPLEV(data->base, 1)) << 32);
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*value = (regval >> cfg->offset) & BIT_MASK(cfg->ngpios);
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return 0;
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}
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static int gpio_bcm2711_port_set_masked_raw(const struct device *port, gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
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struct gpio_bcm2711_data *data = DEV_DATA(port);
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uint64_t regval, regmask;
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uint64_t set, clr;
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value &= BIT_MASK(cfg->ngpios);
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mask &= BIT_MASK(cfg->ngpios);
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regval = (uint64_t)value << cfg->offset;
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regmask = (uint64_t)mask << cfg->offset;
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set = regval & regmask;
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clr = regval ^ regmask;
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sys_write32(FROM_U64(set, 0), GPSET(data->base, 0));
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sys_write32(FROM_U64(clr, 0), GPCLR(data->base, 0));
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sys_write32(FROM_U64(set, 1), GPSET(data->base, 1));
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sys_write32(FROM_U64(clr, 1), GPCLR(data->base, 1));
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return 0;
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}
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static int gpio_bcm2711_port_set_bits_raw(const struct device *port, gpio_port_pins_t pins)
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{
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const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
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struct gpio_bcm2711_data *data = DEV_DATA(port);
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uint64_t regval;
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regval = ((uint64_t)pins & BIT_MASK(cfg->ngpios)) << cfg->offset;
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sys_write32(FROM_U64(regval, 0), GPSET(data->base, 0));
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sys_write32(FROM_U64(regval, 1), GPSET(data->base, 1));
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return 0;
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}
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static int gpio_bcm2711_port_clear_bits_raw(const struct device *port, gpio_port_pins_t pins)
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{
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const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
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struct gpio_bcm2711_data *data = DEV_DATA(port);
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uint64_t regval;
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regval = ((uint64_t)pins & BIT_MASK(cfg->ngpios)) << cfg->offset;
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sys_write32(FROM_U64(regval, 0), GPCLR(data->base, 0));
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sys_write32(FROM_U64(regval, 1), GPCLR(data->base, 1));
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return 0;
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}
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static int gpio_bcm2711_port_toggle_bits(const struct device *port, gpio_port_pins_t pins)
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{
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const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
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struct gpio_bcm2711_data *data = DEV_DATA(port);
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uint64_t regval, regmask;
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uint64_t set, clr;
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regval = ((uint64_t)sys_read32(GPLEV(data->base, 0))) |
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((uint64_t)sys_read32(GPLEV(data->base, 1)) << 32);
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regmask = ((uint64_t)pins & BIT_MASK(cfg->ngpios)) << cfg->offset;
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set = regval ^ regmask;
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clr = regval & regmask;
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sys_write32(FROM_U64(set, 0), GPSET(data->base, 0));
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sys_write32(FROM_U64(clr, 0), GPCLR(data->base, 0));
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sys_write32(FROM_U64(set, 1), GPSET(data->base, 1));
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sys_write32(FROM_U64(clr, 1), GPCLR(data->base, 1));
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return 0;
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}
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static int gpio_bcm2711_pin_interrupt_configure(const struct device *port, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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struct gpio_bcm2711_data *data = DEV_DATA(port);
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uint32_t group;
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uint32_t shift;
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uint32_t regval;
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group = GPIO_REG_GROUP(RPI_PIN_NUM(port, pin), IO_GROUPS);
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shift = GPIO_REG_SHIFT(RPI_PIN_NUM(port, pin), IO_GROUPS, IO_BITS);
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/* Clear all detections first */
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regval = sys_read32(GPREN(data->base, group));
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regval &= ~BIT(shift);
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sys_write32(regval, GPREN(data->base, group));
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regval = sys_read32(GPFEN(data->base, group));
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regval &= ~BIT(shift);
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sys_write32(regval, GPFEN(data->base, group));
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regval = sys_read32(GPHEN(data->base, group));
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regval &= ~BIT(shift);
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sys_write32(regval, GPHEN(data->base, group));
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regval = sys_read32(GPLEN(data->base, group));
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regval &= ~BIT(shift);
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sys_write32(regval, GPLEN(data->base, group));
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regval = sys_read32(GPAREN(data->base, group));
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regval &= ~BIT(shift);
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sys_write32(regval, GPAREN(data->base, group));
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regval = sys_read32(GPAFEN(data->base, group));
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regval &= ~BIT(shift);
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sys_write32(regval, GPAFEN(data->base, group));
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if (mode == GPIO_INT_MODE_LEVEL) {
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if (trig & GPIO_INT_LOW_0) {
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regval = sys_read32(GPLEN(data->base, group));
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regval |= BIT(shift);
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sys_write32(regval, GPLEN(data->base, group));
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}
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if (trig & GPIO_INT_HIGH_1) {
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regval = sys_read32(GPHEN(data->base, group));
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regval |= BIT(shift);
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sys_write32(regval, GPHEN(data->base, group));
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}
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} else if (mode == GPIO_INT_MODE_EDGE) {
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if (trig & GPIO_INT_LOW_0) {
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regval = sys_read32(GPAFEN(data->base, group));
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regval |= BIT(shift);
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sys_write32(regval, GPAFEN(data->base, group));
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}
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if (trig & GPIO_INT_HIGH_1) {
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regval = sys_read32(GPAREN(data->base, group));
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regval |= BIT(shift);
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sys_write32(regval, GPAREN(data->base, group));
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}
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}
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return 0;
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}
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static int gpio_bcm2711_manage_callback(const struct device *port, struct gpio_callback *cb,
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bool set)
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{
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struct gpio_bcm2711_data *data = DEV_DATA(port);
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return gpio_manage_callback(&data->cb, cb, set);
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}
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static void gpio_bcm2711_isr(const struct device *port)
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{
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const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
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struct gpio_bcm2711_data *data = DEV_DATA(port);
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uint64_t regval;
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uint32_t pins;
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regval = ((uint64_t)sys_read32(GPEDS(data->base, 0))) |
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((uint64_t)sys_read32(GPEDS(data->base, 1)) << 32);
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regval &= BIT_MASK(cfg->ngpios) << cfg->offset;
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pins = (uint32_t)(regval >> cfg->offset);
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gpio_fire_callbacks(&data->cb, port, pins);
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/* Write to clear */
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sys_write32(FROM_U64(regval, 0), GPEDS(data->base, 0));
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sys_write32(FROM_U64(regval, 1), GPEDS(data->base, 1));
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}
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int gpio_bcm2711_init(const struct device *port)
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{
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const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
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struct gpio_bcm2711_data *data = DEV_DATA(port);
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DEVICE_MMIO_NAMED_MAP(port, reg_base, K_MEM_CACHE_NONE);
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data->base = DEVICE_MMIO_NAMED_GET(port, reg_base);
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cfg->irq_config_func();
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return 0;
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}
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static const struct gpio_driver_api gpio_bcm2711_api = {
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.pin_configure = gpio_bcm2711_pin_configure,
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.port_get_raw = gpio_bcm2711_port_get_raw,
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.port_set_masked_raw = gpio_bcm2711_port_set_masked_raw,
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.port_set_bits_raw = gpio_bcm2711_port_set_bits_raw,
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.port_clear_bits_raw = gpio_bcm2711_port_clear_bits_raw,
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.port_toggle_bits = gpio_bcm2711_port_toggle_bits,
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.pin_interrupt_configure = gpio_bcm2711_pin_interrupt_configure,
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.manage_callback = gpio_bcm2711_manage_callback,
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};
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#define GPIO_BCM2711_INST(n) \
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static struct gpio_bcm2711_data gpio_bcm2711_data_##n; \
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\
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static void gpio_bcm2711_irq_config_func_##n(void) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), gpio_bcm2711_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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} \
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\
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static const struct gpio_bcm2711_config gpio_bcm2711_cfg_##n = { \
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.common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0)}, \
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DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_INST_PARENT(n)), \
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.irq_config_func = gpio_bcm2711_irq_config_func_##n, \
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.offset = DT_INST_REG_ADDR(n), \
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.ngpios = DT_INST_PROP(n, ngpios), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, gpio_bcm2711_init, NULL, &gpio_bcm2711_data_##n, \
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&gpio_bcm2711_cfg_##n, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_bcm2711_api);
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DT_INST_FOREACH_STATUS_OKAY(GPIO_BCM2711_INST)
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