438 lines
9.4 KiB
C
438 lines
9.4 KiB
C
/*
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* Copyright (c) 2022 BrainCo Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "flash_gd32.h"
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#include <zephyr/logging/log.h>
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#include <zephyr/kernel.h>
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#include <gd32_fmc.h>
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LOG_MODULE_DECLARE(flash_gd32);
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#define GD32_NV_FLASH_V2_NODE DT_INST(0, gd_gd32_nv_flash_v2)
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#define GD32_NV_FLASH_V2_TIMEOUT DT_PROP(GD32_NV_FLASH_V2_NODE, max_erase_time_ms)
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#if !defined(CONFIG_SOC_GD32A503)
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/**
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* @brief GD32 FMC v2 flash memory has 2 banks.
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* Bank0 holds the first 512KB, bank1 is used give capacity for reset.
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* The page size is the same within the same bank, but not equal for all banks.
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*/
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#if (PRE_KB(512) >= SOC_NV_FLASH_SIZE)
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#define GD32_NV_FLASH_V2_BANK0_SIZE SOC_NV_FLASH_SIZE
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#define GD32_NV_FLASH_V2_BANK0_PAGE_SIZE DT_PROP(GD32_NV_FLASH_V2_NODE, bank0_page_size)
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#else
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#define GD32_NV_FLASH_V2_BANK0_SIZE KB(512)
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#define GD32_NV_FLASH_V2_BANK0_PAGE_SIZE DT_PROP(GD32_NV_FLASH_V2_NODE, bank0_page_size)
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#define GD32_NV_FLASH_V2_BANK1_SIZE (SOC_NV_FLASH_SIZE - KB(512))
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#define GD32_NV_FLASH_V2_BANK1_PAGE_SIZE DT_PROP(GD32_NV_FLASH_V2_NODE, bank1_page_size)
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#endif
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#elif defined(CONFIG_SOC_GD32A503)
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/**
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* @brief GD32A503 series flash memory has 2 banks.
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* Bank0 holds the first 256KB, bank1 is used give capacity for reset.
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* The page size is 1KB for all banks.
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*/
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#if (PRE_KB(256) >= SOC_NV_FLASH_SIZE)
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#define GD32_NV_FLASH_V2_BANK0_SIZE SOC_NV_FLASH_SIZE
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#define GD32_NV_FLASH_V2_BANK0_PAGE_SIZE DT_PROP(GD32_NV_FLASH_V2_NODE, bank0_page_size)
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#else
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#define GD32_NV_FLASH_V2_BANK0_SIZE KB(256)
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#define GD32_NV_FLASH_V2_BANK0_PAGE_SIZE DT_PROP(GD32_NV_FLASH_V2_NODE, bank0_page_size)
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#define GD32_NV_FLASH_V2_BANK1_SIZE (SOC_NV_FLASH_SIZE - KB(256))
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#define GD32_NV_FLASH_V2_BANK1_PAGE_SIZE DT_PROP(GD32_NV_FLASH_V2_NODE, bank1_page_size)
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#endif
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#endif
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#define GD32_FMC_V2_BANK0_WRITE_ERR (FMC_STAT0_PGERR | FMC_STAT0_WPERR)
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#define GD32_FMC_V2_BANK0_ERASE_ERR FMC_STAT0_WPERR
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#define GD32_FMC_V2_BANK1_WRITE_ERR (FMC_STAT1_PGERR | FMC_STAT1_WPERR)
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#define GD32_FMC_V2_BANK1_ERASE_ERR FMC_STAT1_WPERR
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#ifdef CONFIG_FLASH_PAGE_LAYOUT
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static struct flash_pages_layout gd32_fmc_v2_layout[] = {
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{
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.pages_size = GD32_NV_FLASH_V2_BANK0_PAGE_SIZE,
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.pages_count = GD32_NV_FLASH_V2_BANK0_SIZE / GD32_NV_FLASH_V2_BANK0_PAGE_SIZE
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},
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#ifdef GD32_NV_FLASH_V2_BANK1_SIZE
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{
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.pages_size = GD32_NV_FLASH_V2_BANK1_PAGE_SIZE,
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.pages_count = GD32_NV_FLASH_V2_BANK1_SIZE / GD32_NV_FLASH_V2_BANK1_PAGE_SIZE
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}
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#endif
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};
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#endif
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static inline void gd32_fmc_v2_bank0_unlock(void)
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{
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FMC_KEY0 = UNLOCK_KEY0;
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FMC_KEY0 = UNLOCK_KEY1;
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}
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static inline void gd32_fmc_v2_bank0_lock(void)
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{
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FMC_CTL0 |= FMC_CTL0_LK;
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}
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static int gd32_fmc_v2_bank0_wait_idle(void)
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{
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const int64_t expired_time = k_uptime_get() + GD32_NV_FLASH_V2_TIMEOUT;
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while (FMC_STAT0 & FMC_STAT0_BUSY) {
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if (k_uptime_get() > expired_time) {
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int gd32_fmc_v2_bank0_write(off_t offset, const void *data, size_t len)
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{
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flash_prg_t *prg_flash = (flash_prg_t *)((uint8_t *)SOC_NV_FLASH_ADDR + offset);
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flash_prg_t *prg_data = (flash_prg_t *)data;
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int ret = 0;
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gd32_fmc_v2_bank0_unlock();
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if (FMC_STAT0 & FMC_STAT0_BUSY) {
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return -EBUSY;
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}
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FMC_CTL0 |= FMC_CTL0_PG;
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for (size_t i = 0U; i < (len / sizeof(flash_prg_t)); i++) {
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*prg_flash++ = *prg_data++;
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}
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ret = gd32_fmc_v2_bank0_wait_idle();
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if (ret < 0) {
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goto expired_out;
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}
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if (FMC_STAT0 & GD32_FMC_V2_BANK0_WRITE_ERR) {
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ret = -EIO;
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FMC_STAT0 |= GD32_FMC_V2_BANK0_WRITE_ERR;
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LOG_ERR("FMC bank0 programming failed");
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}
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expired_out:
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FMC_CTL0 &= ~FMC_CTL0_PG;
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gd32_fmc_v2_bank0_lock();
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return ret;
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}
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static int gd32_fmc_v2_bank0_page_erase(uint32_t page_addr)
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{
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int ret = 0;
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gd32_fmc_v2_bank0_unlock();
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if (FMC_STAT0 & FMC_STAT0_BUSY) {
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return -EBUSY;
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}
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FMC_CTL0 |= FMC_CTL0_PER;
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FMC_ADDR0 = page_addr;
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FMC_CTL0 |= FMC_CTL0_START;
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ret = gd32_fmc_v2_bank0_wait_idle();
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if (ret < 0) {
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goto expired_out;
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}
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if (FMC_STAT0 & GD32_FMC_V2_BANK0_ERASE_ERR) {
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ret = -EIO;
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FMC_STAT0 |= GD32_FMC_V2_BANK0_ERASE_ERR;
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LOG_ERR("FMC bank0 page %u erase failed", page_addr);
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}
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expired_out:
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FMC_CTL0 &= ~FMC_CTL0_PER;
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gd32_fmc_v2_bank0_lock();
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return ret;
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}
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static int gd32_fmc_v2_bank0_erase_block(off_t offset, size_t size)
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{
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uint32_t page_addr = SOC_NV_FLASH_ADDR + offset;
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int ret = 0;
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while (size > 0U) {
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ret = gd32_fmc_v2_bank0_page_erase(page_addr);
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if (ret < 0) {
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return ret;
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}
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size -= GD32_NV_FLASH_V2_BANK0_PAGE_SIZE;
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page_addr += GD32_NV_FLASH_V2_BANK0_PAGE_SIZE;
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}
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return 0;
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}
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#ifdef GD32_NV_FLASH_V2_BANK1_SIZE
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static inline void gd32_fmc_v2_bank1_unlock(void)
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{
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FMC_KEY1 = UNLOCK_KEY0;
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FMC_KEY1 = UNLOCK_KEY1;
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}
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static inline void gd32_fmc_v2_bank1_lock(void)
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{
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FMC_CTL1 |= FMC_CTL1_LK;
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}
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static int gd32_fmc_v2_bank1_wait_idle(void)
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{
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const int64_t expired_time = k_uptime_get() + GD32_NV_FLASH_V2_TIMEOUT;
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while (FMC_STAT1 & FMC_STAT1_BUSY) {
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if (k_uptime_get() > expired_time) {
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int gd32_fmc_v2_bank1_write(off_t offset, const void *data, size_t len)
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{
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flash_prg_t *prg_flash = (flash_prg_t *)((uint8_t *)SOC_NV_FLASH_ADDR + offset);
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flash_prg_t *prg_data = (flash_prg_t *)data;
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int ret = 0;
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gd32_fmc_v2_bank1_unlock();
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if (FMC_STAT1 & FMC_STAT1_BUSY) {
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return -EBUSY;
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}
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FMC_CTL1 |= FMC_CTL1_PG;
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for (size_t i = 0U; i < (len / sizeof(flash_prg_t)); i++) {
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*prg_flash++ = *prg_data++;
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}
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ret = gd32_fmc_v2_bank1_wait_idle();
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if (ret < 0) {
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goto expired_out;
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}
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if (FMC_STAT1 & GD32_FMC_V2_BANK1_WRITE_ERR) {
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ret = -EIO;
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FMC_STAT1 |= GD32_FMC_V2_BANK1_WRITE_ERR;
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LOG_ERR("FMC bank1 programming failed");
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}
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expired_out:
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FMC_CTL1 &= ~FMC_CTL1_PG;
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gd32_fmc_v2_bank1_lock();
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return ret;
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}
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static int gd32_fmc_v2_bank1_page_erase(uint32_t page_addr)
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{
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int ret = 0;
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gd32_fmc_v2_bank1_unlock();
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if (FMC_STAT1 & FMC_STAT1_BUSY) {
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return -EBUSY;
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}
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FMC_CTL1 |= FMC_CTL1_PER;
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FMC_ADDR1 = page_addr;
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FMC_CTL1 |= FMC_CTL1_START;
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ret = gd32_fmc_v2_bank1_wait_idle();
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if (ret < 0) {
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goto expired_out;
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}
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if (FMC_STAT1 & GD32_FMC_V2_BANK1_ERASE_ERR) {
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ret = -EIO;
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FMC_STAT1 |= GD32_FMC_V2_BANK1_ERASE_ERR;
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LOG_ERR("FMC bank1 page %u erase failed", page_addr);
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}
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expired_out:
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FMC_CTL1 &= ~FMC_CTL1_PER;
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gd32_fmc_v2_bank1_lock();
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return ret;
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}
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static int gd32_fmc_v2_bank1_erase_block(off_t offset, size_t size)
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{
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uint32_t page_addr = SOC_NV_FLASH_ADDR + offset;
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int ret = 0;
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while (size > 0U) {
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ret = gd32_fmc_v2_bank1_page_erase(page_addr);
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if (ret < 0) {
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return ret;
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}
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size -= GD32_NV_FLASH_V2_BANK0_SIZE;
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page_addr += GD32_NV_FLASH_V2_BANK0_SIZE;
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}
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return 0;
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}
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#endif /* GD32_NV_FLASH_V2_BANK1_SIZE */
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bool flash_gd32_valid_range(off_t offset, uint32_t len, bool write)
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{
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if ((offset > SOC_NV_FLASH_SIZE) ||
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((offset + len) > SOC_NV_FLASH_SIZE)) {
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return false;
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}
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if (write) {
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/* Check offset and len is flash_prg_t aligned. */
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if ((offset % sizeof(flash_prg_t)) ||
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(len % sizeof(flash_prg_t))) {
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return false;
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}
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} else {
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if (offset < GD32_NV_FLASH_V2_BANK0_SIZE) {
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if (offset % GD32_NV_FLASH_V2_BANK0_PAGE_SIZE) {
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return false;
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}
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if (((offset + len) <= GD32_NV_FLASH_V2_BANK0_SIZE) &&
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(len % GD32_NV_FLASH_V2_BANK0_PAGE_SIZE)) {
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return false;
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}
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}
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#ifdef GD32_NV_FLASH_V2_BANK1_SIZE
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/* Remove bank0 info from offset and len. */
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if ((offset < GD32_NV_FLASH_V2_BANK0_SIZE) &&
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((offset + len) > GD32_NV_FLASH_V2_BANK0_SIZE)) {
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len -= (GD32_NV_FLASH_V2_BANK0_SIZE - offset);
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offset = GD32_NV_FLASH_V2_BANK0_SIZE;
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}
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if (offset >= GD32_NV_FLASH_V2_BANK0_SIZE) {
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if ((offset % GD32_NV_FLASH_V2_BANK1_PAGE_SIZE) ||
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(len % GD32_NV_FLASH_V2_BANK1_PAGE_SIZE)) {
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return false;
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}
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}
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#endif
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}
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return true;
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}
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int flash_gd32_write_range(off_t offset, const void *data, size_t len)
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{
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size_t len0 = 0U;
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int ret = 0;
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if (offset < GD32_NV_FLASH_V2_BANK0_SIZE) {
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if ((offset + len) > GD32_NV_FLASH_V2_BANK0_SIZE) {
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len0 = GD32_NV_FLASH_V2_BANK0_SIZE - offset;
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} else {
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len0 = len;
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}
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ret = gd32_fmc_v2_bank0_write(offset, data, len0);
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if (ret < 0) {
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return ret;
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}
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}
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#ifdef GD32_NV_FLASH_V2_BANK1_SIZE
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size_t len1 = len - len0;
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if (len1 == 0U) {
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return 0;
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}
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/* Will programming bank1, remove bank0 offset. */
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if (offset < GD32_NV_FLASH_V2_BANK0_SIZE) {
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offset = GD32_NV_FLASH_V2_BANK0_SIZE;
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}
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ret = gd32_fmc_v2_bank1_write(offset, data, len1);
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if (ret < 0) {
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return ret;
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}
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#endif
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return 0;
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}
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int flash_gd32_erase_block(off_t offset, size_t size)
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{
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size_t size0 = 0U;
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int ret = 0;
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if (offset < GD32_NV_FLASH_V2_BANK0_SIZE) {
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if ((offset + size0) > GD32_NV_FLASH_V2_BANK0_SIZE) {
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size0 = GD32_NV_FLASH_V2_BANK0_SIZE - offset;
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} else {
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size0 = size;
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}
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ret = gd32_fmc_v2_bank0_erase_block(offset, size0);
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if (ret < 0) {
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return ret;
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}
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}
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#ifdef GD32_NV_FLASH_V2_BANK1_SIZE
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size_t size1 = size - size0;
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if (size1 == 0U) {
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return 0;
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}
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/* Will programming bank1, remove bank0 info from offset. */
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if (offset < GD32_NV_FLASH_V2_BANK0_SIZE) {
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offset = GD32_NV_FLASH_V2_BANK0_SIZE;
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}
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ret = gd32_fmc_v2_bank1_erase_block(offset, size1);
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if (ret < 0) {
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return ret;
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}
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#endif
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return 0;
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}
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#ifdef CONFIG_FLASH_PAGE_LAYOUT
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void flash_gd32_pages_layout(const struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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ARG_UNUSED(dev);
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*layout = gd32_fmc_v2_layout;
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*layout_size = ARRAY_SIZE(gd32_fmc_v2_layout);
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}
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */
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