164 lines
4.1 KiB
C
164 lines
4.1 KiB
C
/*
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*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_utils.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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#if defined(STM32_PLL_ENABLED)
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/**
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* @brief Set up pll configuration
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*/
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__unused
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void config_pll_sysclock(void)
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{
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uint32_t pll_source, pll_mul, pll_div;
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/*
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* PLL MUL
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* 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
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* 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
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* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
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* ...
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* 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
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*/
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pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMUL_Pos);
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/*
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* PLL PREDIV
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* 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
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* 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
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* 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
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* ...
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* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
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*/
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pll_div = STM32_PLL_PREDIV - 1;
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#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
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/*
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* PREDIV1 support is a specific RCC configuration present on
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* following SoCs: STM32F04xx, STM32F07xx, STM32F09xx,
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* STM32F030xC, STM32F302xE, STM32F303xE and STM32F39xx
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* cf Reference manual for more details
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*/
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/* Configure PLL source */
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if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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pll_source = LL_RCC_PLLSOURCE_HSE;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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pll_source = LL_RCC_PLLSOURCE_HSI;
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} else {
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__ASSERT(0, "Invalid source");
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}
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LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul, pll_div);
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#else
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/* Configure PLL source */
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if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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pll_source = LL_RCC_PLLSOURCE_HSE | pll_div;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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pll_source = LL_RCC_PLLSOURCE_HSI_DIV_2;
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} else {
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__ASSERT(0, "Invalid source");
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}
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LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul);
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#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
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}
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/**
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* @brief Return pllout frequency
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*/
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__unused
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uint32_t get_pllout_frequency(void)
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{
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uint32_t pll_input_freq, pll_mul, pll_div;
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/*
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* PLL MUL
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* 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
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* 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
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* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
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* ...
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* 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
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*/
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pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMUL_Pos);
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/*
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* PLL PREDIV
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* 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
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* 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
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* 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
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* ...
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* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
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*/
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pll_div = STM32_PLL_PREDIV - 1;
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#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
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/*
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* PREDIV1 support is a specific RCC configuration present on
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* following SoCs: STM32F04xx, STM32F07xx, STM32F09xx,
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* STM32F030xC, STM32F302xE, STM32F303xE and STM32F39xx
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* cf Reference manual for more details
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*/
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/* Configure PLL source */
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if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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pll_input_freq = STM32_HSE_FREQ;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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pll_input_freq = STM32_HSI_FREQ;
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} else {
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return 0;
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}
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return __LL_RCC_CALC_PLLCLK_FREQ(pll_input_freq, pll_mul, pll_div);
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#else
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/* Configure PLL source */
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if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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pll_input_freq = STM32_HSE_FREQ;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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pll_input_freq = STM32_HSI_FREQ / 2;
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} else {
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return 0;
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}
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return __LL_RCC_CALC_PLLCLK_FREQ(pll_input_freq, pll_mul);
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#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
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}
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#endif /* defined(STM32_PLL_ENABLED) */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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/* Enable PWR clock, required to access BDCR and PWR_CR */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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#ifndef CONFIG_SOC_SERIES_STM32F3X
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#if defined(CONFIG_EXTI_STM32) || defined(CONFIG_USB_DC_STM32)
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/* Enable System Configuration Controller clock. */
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
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#endif
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#else
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#if defined(CONFIG_USB_DC_STM32) && defined(SYSCFG_CFGR1_USB_IT_RMP)
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/* Enable System Configuration Controller clock. */
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/* SYSCFG is required to remap IRQ to avoid conflicts with CAN */
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/* cf §14.1.3, RM0316 */
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
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#endif
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#endif /* !CONFIG_SOC_SERIES_STM32F3X */
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}
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