288 lines
8.0 KiB
C
288 lines
8.0 KiB
C
/*
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* Copyright (c) 2023 EPAM Systems
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* Copyright (c) 2023 IoT.bzh
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*
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* r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_r8a779f0_cpg_mssr
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#include <errno.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
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#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
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#include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
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#include <zephyr/irq.h>
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#include "clock_control_renesas_cpg_mssr.h"
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#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_DECLARE(clock_control_rcar);
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#define R8A779F0_CLK_SD0_STOP_BIT 8
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#define R8A779F0_CLK_SD0_DIV_MASK 0x3
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#define R8A779F0_CLK_SD0_DIV_SHIFT 0
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#define R8A779F0_CLK_SD0H_STOP_BIT 9
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#define R8A779F0_CLK_SD0H_DIV_MASK 0x7
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#define R8A779F0_CLK_SD0H_DIV_SHIFT 2
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#define R8A779F0_CLK_SDSRC_DIV_MASK 0x3
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#define R8A779F0_CLK_SDSRC_DIV_SHIFT 29
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struct r8a779f0_cpg_mssr_cfg {
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DEVICE_MMIO_ROM; /* Must be first */
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};
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struct r8a779f0_cpg_mssr_data {
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struct rcar_cpg_mssr_data cmn; /* Must be first */
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};
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A779F0_CLK_OSC,
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/* Internal Core Clocks */
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CLK_PLL5,
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CLK_SDSRC,
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};
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/* NOTE: the array MUST be sorted by module field */
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static struct cpg_clk_info_table core_props[] = {
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RCAR_CORE_CLK_INFO_ITEM(R8A779F0_CLK_S0D12_PER, RCAR_CPG_NONE, RCAR_CPG_NONE,
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RCAR_CPG_KHZ(66660)),
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RCAR_CORE_CLK_INFO_ITEM(R8A779F0_CLK_CL16M, RCAR_CPG_NONE, RCAR_CPG_NONE,
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RCAR_CPG_KHZ(16660)),
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RCAR_CORE_CLK_INFO_ITEM(R8A779F0_CLK_SD0H, 0x0870, CLK_SDSRC, RCAR_CPG_NONE),
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RCAR_CORE_CLK_INFO_ITEM(R8A779F0_CLK_SD0, 0x0870, R8A779F0_CLK_SD0H, RCAR_CPG_NONE),
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RCAR_CORE_CLK_INFO_ITEM(R8A779F0_CLK_SASYNCPERD1, RCAR_CPG_NONE, RCAR_CPG_NONE,
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266666666),
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RCAR_CORE_CLK_INFO_ITEM(CLK_PLL5, RCAR_CPG_NONE, RCAR_CPG_NONE, RCAR_CPG_MHZ(3200)),
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RCAR_CORE_CLK_INFO_ITEM(CLK_SDSRC, 0x08A4, CLK_PLL5, RCAR_CPG_NONE),
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};
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/* NOTE: the array MUST be sorted by module field */
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static struct cpg_clk_info_table mod_props[] = {
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RCAR_MOD_CLK_INFO_ITEM(514, R8A779F0_CLK_SASYNCPERD1),
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RCAR_MOD_CLK_INFO_ITEM(702, R8A779F0_CLK_S0D12_PER),
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RCAR_MOD_CLK_INFO_ITEM(704, R8A779F0_CLK_S0D12_PER),
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RCAR_MOD_CLK_INFO_ITEM(706, R8A779F0_CLK_SD0),
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RCAR_MOD_CLK_INFO_ITEM(915, R8A779F0_CLK_CL16M),
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};
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static int r8a779f0_cpg_enable_disable_core(const struct device *dev,
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struct cpg_clk_info_table *clk_info, uint32_t enable)
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{
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int ret = 0;
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uint32_t reg;
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switch (clk_info->module) {
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case R8A779F0_CLK_SD0:
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reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset);
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reg &= ~(1 << R8A779F0_CLK_SD0_STOP_BIT);
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reg |= (!enable << R8A779F0_CLK_SD0_STOP_BIT);
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break;
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case R8A779F0_CLK_SD0H:
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reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset);
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reg &= ~(1 << R8A779F0_CLK_SD0H_STOP_BIT);
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reg |= (!enable << R8A779F0_CLK_SD0H_STOP_BIT);
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break;
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default:
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ret = -ENOTSUP;
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break;
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}
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if (!ret) {
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rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg);
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}
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return ret;
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}
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static int r8a779f0_cpg_core_clock_endisable(const struct device *dev, struct rcar_cpg_clk *clk,
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bool enable)
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{
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struct cpg_clk_info_table *clk_info;
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struct r8a779f0_cpg_mssr_data *data = dev->data;
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k_spinlock_key_t key;
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clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module);
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if (!clk_info) {
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return -EINVAL;
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}
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if (enable) {
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if (clk->rate > 0) {
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int ret;
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uintptr_t rate = clk->rate;
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ret = rcar_cpg_set_rate(dev, (clock_control_subsys_t)clk,
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(clock_control_subsys_rate_t)rate);
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if (ret < 0) {
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return ret;
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}
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}
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}
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key = k_spin_lock(&data->cmn.lock);
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r8a779f0_cpg_enable_disable_core(dev, clk_info, enable);
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k_spin_unlock(&data->cmn.lock, key);
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return 0;
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}
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int r8a779f0_cpg_mssr_start_stop(const struct device *dev, clock_control_subsys_t sys, bool enable)
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{
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struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys;
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int ret;
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if (!dev || !sys) {
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return -EINVAL;
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}
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if (clk->domain == CPG_MOD) {
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struct r8a779f0_cpg_mssr_data *data = dev->data;
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k_spinlock_key_t key;
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key = k_spin_lock(&data->cmn.lock);
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ret = rcar_cpg_mstp_clock_endisable(DEVICE_MMIO_GET(dev), clk->module, enable);
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k_spin_unlock(&data->cmn.lock, key);
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} else if (clk->domain == CPG_CORE) {
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ret = r8a779f0_cpg_core_clock_endisable(dev, clk, enable);
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} else {
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ret = -EINVAL;
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}
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return ret;
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}
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static uint32_t r8a779f0_get_div_helper(uint32_t reg_val, uint32_t module)
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{
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switch (module) {
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case R8A779F0_CLK_S0D12_PER:
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case R8A779F0_CLK_CL16M:
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return 1;
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case CLK_SDSRC:
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reg_val >>= R8A779F0_CLK_SDSRC_DIV_SHIFT;
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reg_val &= R8A779F0_CLK_SDSRC_DIV_MASK;
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/* setting of 3 is prohibited */
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if (reg_val < 3) {
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/* real divider is in range 4 - 6 */
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return reg_val + 4;
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}
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LOG_WRN("SDSRC clock has an incorrect divider value: %u", reg_val);
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return RCAR_CPG_NONE;
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case R8A779F0_CLK_SD0H:
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reg_val >>= R8A779F0_CLK_SD0H_DIV_SHIFT;
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reg_val &= R8A779F0_CLK_SD0H_DIV_MASK;
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/* setting of value bigger than 4 is prohibited */
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if (reg_val < 5) {
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return (1 << reg_val);
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}
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LOG_WRN("SD0H clock has an incorrect divider value: %u", reg_val);
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return RCAR_CPG_NONE;
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case R8A779F0_CLK_SD0:
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/* convert only two possible values 0,1 to 2,4 */
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return (1 << ((reg_val & R8A779F0_CLK_SD0_DIV_MASK) + 1));
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default:
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return RCAR_CPG_NONE;
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}
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}
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static int r8a779f0_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask)
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{
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switch (module) {
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case CLK_SDSRC:
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/* divider has to be in range 4-6 */
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if (*divider > 3 && *divider < 7) {
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/* we can write to register value in range 0-2 */
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*divider -= 4;
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*divider <<= R8A779F0_CLK_SDSRC_DIV_SHIFT;
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*div_mask = R8A779F0_CLK_SDSRC_DIV_MASK << R8A779F0_CLK_SDSRC_DIV_SHIFT;
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return 0;
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}
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return -EINVAL;
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case R8A779F0_CLK_SD0:
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/* possible to have only 2 or 4 */
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if (*divider == 2 || *divider == 4) {
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/* convert 2/4 to 0/1 */
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*divider >>= 2;
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*div_mask = R8A779F0_CLK_SD0_DIV_MASK << R8A779F0_CLK_SD0_DIV_SHIFT;
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return 0;
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}
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return -EINVAL;
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case R8A779F0_CLK_SD0H:
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/* divider should be power of two number and last possible value 16 */
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if (!is_power_of_two(*divider) || *divider > 16) {
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return -EINVAL;
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}
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/* 1,2,4,8,16 have to be converted to 0,1,2,3,4 and then shifted */
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*divider = (find_lsb_set(*divider) - 1) << R8A779F0_CLK_SD0H_DIV_SHIFT;
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*div_mask = R8A779F0_CLK_SD0H_DIV_MASK << R8A779F0_CLK_SD0H_DIV_SHIFT;
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return 0;
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default:
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return -ENOTSUP;
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}
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}
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static int r8a779f0_cpg_mssr_start(const struct device *dev, clock_control_subsys_t sys)
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{
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return r8a779f0_cpg_mssr_start_stop(dev, sys, true);
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}
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static int r8a779f0_cpg_mssr_stop(const struct device *dev, clock_control_subsys_t sys)
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{
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return r8a779f0_cpg_mssr_start_stop(dev, sys, false);
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}
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static int r8a779f0_cpg_mssr_init(const struct device *dev)
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{
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DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
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rcar_cpg_build_clock_relationship(dev);
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rcar_cpg_update_all_in_out_freq(dev);
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return 0;
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}
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static const struct clock_control_driver_api r8a779f0_cpg_mssr_api = {
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.on = r8a779f0_cpg_mssr_start,
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.off = r8a779f0_cpg_mssr_stop,
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.get_rate = rcar_cpg_get_rate,
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.set_rate = rcar_cpg_set_rate,
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};
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#define R8A779F0_MSSR_INIT(inst) \
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static struct r8a779f0_cpg_mssr_cfg cpg_mssr##inst##_cfg = { \
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DEVICE_MMIO_ROM_INIT(DT_DRV_INST(inst)), \
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}; \
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\
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static struct r8a779f0_cpg_mssr_data cpg_mssr##inst##_data = { \
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.cmn.clk_info_table[CPG_CORE] = core_props, \
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.cmn.clk_info_table_size[CPG_CORE] = ARRAY_SIZE(core_props), \
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.cmn.clk_info_table[CPG_MOD] = mod_props, \
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.cmn.clk_info_table_size[CPG_MOD] = ARRAY_SIZE(mod_props), \
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.cmn.get_div_helper = r8a779f0_get_div_helper, \
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.cmn.set_rate_helper = r8a779f0_set_rate_helper \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, \
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&r8a779f0_cpg_mssr_init, \
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NULL, \
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&cpg_mssr##inst##_data, \
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&cpg_mssr##inst##_cfg, \
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PRE_KERNEL_1, \
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \
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&r8a779f0_cpg_mssr_api);
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DT_INST_FOREACH_STATUS_OKAY(R8A779F0_MSSR_INIT)
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