100 lines
2.8 KiB
Plaintext
100 lines
2.8 KiB
Plaintext
# Nordic Semiconductor nRF54 MCU line
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_NRF54LX
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select SOC_COMPATIBLE_NRF54LX
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select HAS_NRFX
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select HAS_NORDIC_DRIVERS
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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config SOC_NRF54L15_ENGA_CPUAPP
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select ARM
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select ARMV8_M_DSP
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ICACHE
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select CPU_HAS_ARM_SAU
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select CPU_HAS_FPU
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select HAS_HW_NRF_RADIO_IEEE802154
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select HAS_POWEROFF
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config SOC_NRF54L15_CPUAPP
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select ARM
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select ARMV8_M_DSP
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ICACHE
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select CPU_HAS_ARM_SAU
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select CPU_HAS_FPU
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select HAS_HW_NRF_RADIO_IEEE802154
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select HAS_POWEROFF
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config SOC_NRF54L20_ENGA_CPUAPP
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select ARM
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select ARMV8_M_DSP
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ICACHE
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select CPU_HAS_ARM_SAU
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select CPU_HAS_FPU
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select HAS_HW_NRF_RADIO_IEEE802154
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select HAS_POWEROFF
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config SOC_NRF54L15_ENGA_CPUFLPR
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depends on RISCV_CORE_NORDIC_VPR
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config SOC_NRF54L15_CPUFLPR
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depends on RISCV_CORE_NORDIC_VPR
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if SOC_SERIES_NRF54LX
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config SOC_NRF54LX_SKIP_CLOCK_CONFIG
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bool "Skip clock frequency configuration in system initialization"
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help
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With this option, the CPU clock frequency is not set during system initialization.
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The CPU runs with the default, hardware-selected frequency.
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config SOC_NRF54LX_DISABLE_FICR_TRIMCNF
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bool "Disable trimming of the device"
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default y if TRUSTED_EXECUTION_NONSECURE
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help
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Disable trimming of the device. When the device is trimmed it
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will copy all the trimming values from FICR into the target
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addresses.
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config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE
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bool "Skip disabling glitch detector"
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default y if TRUSTED_EXECUTION_NONSECURE
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help
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With this option, the glitch detector is not disabled during system initialization.
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The CPU runs with the default state of glitch detector.
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config SOC_NRF_FORCE_CONSTLAT
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bool "Force constant-latency mode"
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help
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In constant latency mode the CPU wakeup latency and the PPI task response
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will be constant and kept at a minimum. This is secured by forcing a set
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of base resources on while in sleep. The advantage of having a constant
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and predictable latency will be at the cost of having increased power consumption.
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config SOC_NRF54L_NORMAL_VOLTAGE_MODE
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bool "NRF54L Normal Voltage Mode."
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if NRF_GRTC_TIMER
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config ELV_GRTC_LFXO_ALLOWED
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bool
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depends on NRF_GRTC_SLEEP_ALLOWED
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select EXPERIMENTAL
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help
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This feature allows using ELV mode when GRTC operates with the LFXO as
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a low-frequency clock source. The LFXO is automatically activated when
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preparing to system-off.
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WARNING! This feature is EXPERIMENTAL and may brick your device!
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endif # NRF_GRTC_TIMER
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endif # SOC_SERIES_NRF54LX
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