82 lines
1.8 KiB
C
82 lines
1.8 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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* Description:
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* Adding support for Cyclone V SoC FPGA, buildi mmu table,
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* creating function to reserve the vector memory area
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*/
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/init.h>
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#include <zephyr/sys/util.h>
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#include <mmu.h>
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#include <zephyr/arch/arm/mmu/arm_mmu.h>
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#include "soc.h"
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#include <cmsis_core.h>
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void arch_reserved_pages_update(void)
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{
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/* Function created to reserve the vector table */
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uintptr_t addr = 0;
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size_t len = 0x1000;
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uintptr_t pos = ROUND_DOWN(addr, CONFIG_MMU_PAGE_SIZE);
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uintptr_t end = ROUND_UP(addr + len, CONFIG_MMU_PAGE_SIZE);
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for (; pos < end; pos += CONFIG_MMU_PAGE_SIZE) {
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if (!k_mem_is_page_frame(pos)) {
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continue;
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}
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struct k_mem_page_frame *pf = k_mem_phys_to_page_frame(pos);
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k_mem_page_frame_set(pf, K_MEM_PAGE_FRAME_RESERVED);
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}
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}
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static const struct arm_mmu_region mmu_regions[] = {
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MMU_REGION_FLAT_ENTRY("vectors",
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0x00000000,
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0x1000,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
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MMU_REGION_FLAT_ENTRY("mpcore",
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0xF8F00000,
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0x2000,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
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MMU_REGION_FLAT_ENTRY("devices",
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0xFF000000,
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0x1000000,
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MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W
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/* Adding Executable property to devices when using for testing */
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#ifndef CONFIG_ASSERT
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| MPERM_X
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#endif
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),
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};
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const struct arm_mmu_config mmu_config = {
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.num_regions = ARRAY_SIZE(mmu_regions),
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.mmu_regions = mmu_regions,
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};
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/**
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* @brief Basic hardware initialization of the Cyclone V SoC FPGA
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*
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* Performs the basic initialization of the Cyclone V SoC FPGA.
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*
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* @return 0
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*/
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void soc_early_init_hook(void)
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{
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unsigned int sctlr = __get_SCTLR(); /* modifying some registers prior to initialization */
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sctlr &= ~SCTLR_A_Msk;
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__set_SCTLR(sctlr);
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__set_VBAR(0);
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}
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/* EOF */
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