109 lines
2.4 KiB
C
109 lines
2.4 KiB
C
/* Copyright (c) 2023 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __ZEPHYR_CAVS_LIB_ASM_LDO_MANAGEMENT_H__
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#define __ZEPHYR_CAVS_LIB_ASM_LDO_MANAGEMENT_H__
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#ifdef _ASMLANGUAGE
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#define SHIM_BASE 0x00071F00
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#define SHIM_LDOCTL 0xA4
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#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0 | 3 << 16)
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#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
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#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16)
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#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
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#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0)
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#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2)
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#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS (BIT(0) | BIT(16))
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#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
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.macro m_cavs_set_ldo_state state, ax
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movi \ax, (SHIM_BASE + SHIM_LDOCTL)
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s32i \state, \ax, 0
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memw
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/* wait loop > 300ns (min 100ns required) */
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movi \ax, 128
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1 :
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addi \ax, \ax, -1
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nop
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bnez \ax, 1b
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.endm
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.macro m_cavs_set_hpldo_state state, ax, ay
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movi \ax, (SHIM_BASE + SHIM_LDOCTL)
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l32i \ay, \ax, 0
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movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK)
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and \ay, \ax, \ay
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or \state, \ay, \state
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m_cavs_set_ldo_state \state, \ax
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.endm
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.macro m_cavs_set_lpldo_state state, ax, ay
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movi \ax, (SHIM_BASE + SHIM_LDOCTL)
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l32i \ay, \ax, 0
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/* LP SRAM mask */
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movi \ax, ~(SHIM_LDOCTL_LPSRAM_MASK)
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and \ay, \ax, \ay
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or \state, \ay, \state
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m_cavs_set_ldo_state \state, \ax
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.endm
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.macro m_cavs_set_ldo_on_state ax, ay, az
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movi \ay, (SHIM_BASE + SHIM_LDOCTL)
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l32i \az, \ay, 0
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movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
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and \az, \ax, \az
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movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_ON | SHIM_LDOCTL_LPSRAM_LDO_ON)
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or \ax, \az, \ax
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m_cavs_set_ldo_state \ax, \ay
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.endm
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.macro m_cavs_set_ldo_off_state ax, ay, az
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/* wait loop > 300ns (min 100ns required) */
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movi \ax, 128
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1 :
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addi \ax, \ax, -1
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nop
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bnez \ax, 1b
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movi \ay, (SHIM_BASE + SHIM_LDOCTL)
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l32i \az, \ay, 0
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movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
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and \az, \az, \ax
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movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_OFF | SHIM_LDOCTL_LPSRAM_LDO_OFF)
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or \ax, \ax, \az
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s32i \ax, \ay, 0
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l32i \ax, \ay, 0
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.endm
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.macro m_cavs_set_ldo_bypass_state ax, ay, az
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/* wait loop > 300ns (min 100ns required) */
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movi \ax, 128
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1 :
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addi \ax, \ax, -1
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nop
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bnez \ax, 1b
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movi \ay, (SHIM_BASE + SHIM_LDOCTL)
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l32i \az, \ay, 0
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movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
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and \az, \az, \ax
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movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_BYPASS | SHIM_LDOCTL_LPSRAM_LDO_BYPASS)
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or \ax, \ax, \az
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s32i \ax, \ay, 0
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l32i \ax, \ay, 0
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.endm
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#endif
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#endif /* __ZEPHYR_CAVS_LIB_ASM_LDO_MANAGEMENT_H__ */
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