34 lines
624 B
C
34 lines
624 B
C
/*
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* Copyright 2024 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <fsl_common.h>
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uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate)
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{
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/* PLL0 is set to 150 MHz */
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uint32_t pll_rate = 150000000;
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uint8_t divider;
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/* Disable the FLEXSPI clock */
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SYSCON->FLEXSPICLKSEL = 0;
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divider = ((pll_rate + (rate - 1)) / rate) - 1;
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/* Max divider value is 8 */
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divider = MIN(divider, 8);
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SYSCON->FLEXSPICLKDIV = divider;
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/* Switch FLEXSPI to PLL0 */
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SYSCON->FLEXSPICLKSEL = 1;
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return 0;
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}
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void flexspi_clock_safe_config(void)
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{
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/* Switch FLEXSPI to FRO_HF */
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SYSCON->FLEXSPICLKSEL = 3;
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}
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