42 lines
1.1 KiB
Plaintext
42 lines
1.1 KiB
Plaintext
/*
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* Copyright (c) 2019 Vestas Wind Systems A/S
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <nxp/nxp_ke1xf.dtsi>
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/ {
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/* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
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* contiguous block in the memory map, however misaligned accesses
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* across the 0x2000_0000 boundary are not supported in the Arm
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* Cortex-M4 architecture. For clarity and to avoid the temptation for
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* someone to extend sram0 without solving this issue, we define two
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* separate memory nodes here and only use the upper one for now. A
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* potential solution has been proposed in binutils:
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* https://sourceware.org/ml/binutils/2017-02/msg00250.html
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*/
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sram_l: memory@1fffc000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x1fffc000 DT_SIZE_K(16)>;
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(16)>;
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};
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};
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&flash_controller {
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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label = "MCUX_FLASH";
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reg = <0 DT_SIZE_K(256)>;
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erase-block-size = <DT_SIZE_K(4)>;
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write-block-size = <8>;
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};
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};
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