406 lines
11 KiB
C
406 lines
11 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2017 RnDity Sp. z o.o.
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* Copyright (c) 2019-23 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Driver for External interrupt/event controller in STM32 MCUs
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*/
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#define EXTI_NODE DT_INST(0, st_stm32_exti)
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#include <zephyr/device.h>
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_gpio.h> /* For STM32F1 series */
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#include <stm32_ll_exti.h>
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#include <stm32_ll_system.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h> /* For STM32L0 series */
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#include <zephyr/drivers/interrupt_controller/gpio_intc_stm32.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/irq.h>
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#include "stm32_hsem.h"
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/** @brief EXTI lines range mapped to a single interrupt line */
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struct stm32_exti_range {
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/** Start of the range */
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uint8_t start;
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/** Range length */
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uint8_t len;
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};
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#define NUM_EXTI_LINES DT_PROP(DT_NODELABEL(exti), num_lines)
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static IRQn_Type exti_irq_table[NUM_EXTI_LINES] = {[0 ... NUM_EXTI_LINES - 1] = 0xFF};
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/* User callback wrapper */
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struct __exti_cb {
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stm32_gpio_irq_cb_t cb;
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void *data;
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};
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/* EXTI driver data */
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struct stm32_exti_data {
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/* per-line callbacks */
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struct __exti_cb cb[NUM_EXTI_LINES];
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};
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/**
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* @returns the LL_<PPP>_EXTI_LINE_xxx define that corresponds to specified @p linenum
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* This value can be used with the LL EXTI source configuration functions.
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*/
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static inline uint32_t stm32_exti_linenum_to_src_cfg_line(gpio_pin_t linenum)
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{
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#if defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X)
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return ((linenum % 4 * 4) << 16) | (linenum / 4);
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti)
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return ((linenum & 0x3) << (16 + 3)) | (linenum >> 2);
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7rs_exti)
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/* Gives the LL_SBS_EXTI_LINEn corresponding to the line number */
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return (((linenum % 4 * 4) << LL_SBS_REGISTER_PINPOS_SHFT) | (linenum / 4));
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#else
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return (0xF << ((linenum % 4 * 4) + 16)) | (linenum / 4);
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#endif
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}
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/**
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* @brief Checks interrupt pending bit for specified EXTI line
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*
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* @param line EXTI line number
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*/
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static inline int stm32_exti_is_pending(stm32_gpio_irq_line_t line)
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{
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti)
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return (LL_EXTI_IsActiveRisingFlag_0_31(line) ||
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LL_EXTI_IsActiveFallingFlag_0_31(line));
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#elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
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return LL_C2_EXTI_IsActiveFlag_0_31(line);
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#else
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return LL_EXTI_IsActiveFlag_0_31(line);
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#endif
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}
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/**
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* @brief Clears interrupt pending bit for specified EXTI line
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*
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* @param line EXTI line number
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*/
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static inline void stm32_exti_clear_pending(stm32_gpio_irq_line_t line)
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{
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti)
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LL_EXTI_ClearRisingFlag_0_31(line);
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LL_EXTI_ClearFallingFlag_0_31(line);
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#elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
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LL_C2_EXTI_ClearFlag_0_31(line);
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#else
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LL_EXTI_ClearFlag_0_31(line);
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#endif
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}
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/**
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* @returns the LL_EXTI_LINE_n define for EXTI line number @p linenum
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*/
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static inline stm32_gpio_irq_line_t linenum_to_ll_exti_line(gpio_pin_t linenum)
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{
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return BIT(linenum);
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}
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/**
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* @returns EXTI line number for LL_EXTI_LINE_n define
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*/
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static inline gpio_pin_t ll_exti_line_to_linenum(stm32_gpio_irq_line_t line)
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{
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return LOG2(line);
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}
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/**
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* @brief EXTI ISR handler
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*
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* Check EXTI lines in exti_range for pending interrupts
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*
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* @param exti_range Pointer to a exti_range structure
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*/
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static void stm32_exti_isr(const void *exti_range)
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{
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const struct device *dev = DEVICE_DT_GET(EXTI_NODE);
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struct stm32_exti_data *data = dev->data;
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const struct stm32_exti_range *range = exti_range;
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stm32_gpio_irq_line_t line;
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uint32_t line_num;
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/* see which bits are set */
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for (uint8_t i = 0; i <= range->len; i++) {
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line_num = range->start + i;
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line = linenum_to_ll_exti_line(line_num);
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/* check if interrupt is pending */
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if (stm32_exti_is_pending(line) != 0) {
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/* clear pending interrupt */
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stm32_exti_clear_pending(line);
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/* run callback only if one is registered */
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if (!data->cb[line_num].cb) {
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continue;
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}
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/* `line` can be passed as-is because LL_EXTI_LINE_n is (1 << n) */
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data->cb[line_num].cb(line, data->cb[line_num].data);
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}
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}
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}
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/** Enables the peripheral clock required to access EXTI registers */
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static int stm32_exti_enable_registers(void)
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{
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/* Initialize to 0 for series where there is nothing to do. */
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int ret = 0;
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#if defined(CONFIG_SOC_SERIES_STM32F2X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32F4X) || \
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defined(CONFIG_SOC_SERIES_STM32F7X) || \
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defined(CONFIG_SOC_SERIES_STM32H7X) || \
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defined(CONFIG_SOC_SERIES_STM32H7RSX) || \
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defined(CONFIG_SOC_SERIES_STM32L1X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X)
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const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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struct stm32_pclken pclken = {
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#if defined(CONFIG_SOC_SERIES_STM32H7X)
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.bus = STM32_CLOCK_BUS_APB4,
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.enr = LL_APB4_GRP1_PERIPH_SYSCFG
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#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
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.bus = STM32_CLOCK_BUS_APB4,
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.enr = LL_APB4_GRP1_PERIPH_SBS
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#else
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.bus = STM32_CLOCK_BUS_APB2,
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.enr = LL_APB2_GRP1_PERIPH_SYSCFG
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#endif /* CONFIG_SOC_SERIES_STM32H7X */
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};
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ret = clock_control_on(clk, (clock_control_subsys_t) &pclken);
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#endif
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return ret;
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}
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static void stm32_fill_irq_table(int8_t start, int8_t len, int32_t irqn)
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{
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for (int i = 0; i < len; i++) {
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exti_irq_table[start + i] = irqn;
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}
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}
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/* This macro:
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* - populates line_range_x from line_range dt property
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* - fill exti_irq_table through stm32_fill_irq_table()
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* - calls IRQ_CONNECT for each interrupt and matching line_range
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*/
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#define STM32_EXTI_INIT_LINE_RANGE(node_id, interrupts, idx) \
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static const struct stm32_exti_range line_range_##idx = { \
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DT_PROP_BY_IDX(node_id, line_ranges, UTIL_X2(idx)), \
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DT_PROP_BY_IDX(node_id, line_ranges, UTIL_INC(UTIL_X2(idx))) \
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}; \
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stm32_fill_irq_table(line_range_##idx.start, \
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line_range_##idx.len, \
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DT_IRQ_BY_IDX(node_id, idx, irq)); \
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IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, idx, irq), \
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DT_IRQ_BY_IDX(node_id, idx, priority), \
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stm32_exti_isr, &line_range_##idx, 0);
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/**
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* @brief Initializes the EXTI GPIO interrupt controller driver
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*/
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static int stm32_exti_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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DT_FOREACH_PROP_ELEM(DT_NODELABEL(exti),
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interrupt_names,
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STM32_EXTI_INIT_LINE_RANGE);
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return stm32_exti_enable_registers();
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}
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static struct stm32_exti_data exti_data;
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DEVICE_DT_DEFINE(EXTI_NODE, &stm32_exti_init,
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NULL,
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&exti_data, NULL,
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PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY,
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NULL);
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/**
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* @brief EXTI GPIO interrupt controller API implementation
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*/
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/**
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* @internal
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* STM32 EXTI driver:
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* The type @ref stm32_gpio_irq_line_t is used to hold the LL_EXTI_LINE_xxx
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* defines of the LL EXTI API that corresponds to the provided pin.
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*
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* The port is not part of these definitions because port configuration
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* is done via different APIs, which use the LL_<PPP>_EXTI_LINE_xxx defines
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* returned by @ref stm32_exti_linenum_to_src_cfg_line instead.
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* @endinternal
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*/
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stm32_gpio_irq_line_t stm32_gpio_intc_get_pin_irq_line(uint32_t port, gpio_pin_t pin)
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{
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ARG_UNUSED(port);
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return linenum_to_ll_exti_line(pin);
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}
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void stm32_gpio_intc_enable_line(stm32_gpio_irq_line_t line)
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{
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unsigned int irqnum;
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uint32_t line_num = ll_exti_line_to_linenum(line);
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__ASSERT_NO_MSG(line_num < NUM_EXTI_LINES);
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/* Get matching exti irq provided line thanks to irq_table */
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irqnum = exti_irq_table[line_num];
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__ASSERT_NO_MSG(irqnum != 0xFF);
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/* Enable requested line interrupt */
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#if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
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LL_C2_EXTI_EnableIT_0_31(line);
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#else
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LL_EXTI_EnableIT_0_31(line);
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#endif
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/* Enable exti irq interrupt */
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irq_enable(irqnum);
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}
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void stm32_gpio_intc_disable_line(stm32_gpio_irq_line_t line)
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{
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#if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
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LL_C2_EXTI_DisableIT_0_31(line);
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#else
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LL_EXTI_DisableIT_0_31(line);
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#endif
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}
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void stm32_gpio_intc_select_line_trigger(stm32_gpio_irq_line_t line, uint32_t trg)
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{
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z_stm32_hsem_lock(CFG_HW_EXTI_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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switch (trg) {
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case STM32_GPIO_IRQ_TRIG_NONE:
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LL_EXTI_DisableRisingTrig_0_31(line);
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LL_EXTI_DisableFallingTrig_0_31(line);
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break;
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case STM32_GPIO_IRQ_TRIG_RISING:
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LL_EXTI_EnableRisingTrig_0_31(line);
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LL_EXTI_DisableFallingTrig_0_31(line);
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break;
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case STM32_GPIO_IRQ_TRIG_FALLING:
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LL_EXTI_EnableFallingTrig_0_31(line);
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LL_EXTI_DisableRisingTrig_0_31(line);
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break;
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case STM32_GPIO_IRQ_TRIG_BOTH:
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LL_EXTI_EnableRisingTrig_0_31(line);
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LL_EXTI_EnableFallingTrig_0_31(line);
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break;
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default:
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__ASSERT_NO_MSG(0);
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break;
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}
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z_stm32_hsem_unlock(CFG_HW_EXTI_SEMID);
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}
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int stm32_gpio_intc_set_irq_callback(stm32_gpio_irq_line_t line, stm32_gpio_irq_cb_t cb, void *user)
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{
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const struct device *const dev = DEVICE_DT_GET(EXTI_NODE);
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struct stm32_exti_data *data = dev->data;
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uint32_t line_num = ll_exti_line_to_linenum(line);
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if ((data->cb[line_num].cb == cb) && (data->cb[line_num].data == user)) {
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return 0;
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}
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/* if callback already exists/maybe-running return busy */
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if (data->cb[line_num].cb != NULL) {
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return -EBUSY;
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}
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data->cb[line_num].cb = cb;
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data->cb[line_num].data = user;
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return 0;
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}
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void stm32_gpio_intc_remove_irq_callback(stm32_gpio_irq_line_t line)
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{
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const struct device *const dev = DEVICE_DT_GET(EXTI_NODE);
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struct stm32_exti_data *data = dev->data;
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uint32_t line_num = ll_exti_line_to_linenum(line);
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data->cb[line_num].cb = NULL;
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data->cb[line_num].data = NULL;
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}
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void stm32_exti_set_line_src_port(gpio_pin_t line, uint32_t port)
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{
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uint32_t ll_line = stm32_exti_linenum_to_src_cfg_line(line);
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#if defined(CONFIG_SOC_SERIES_STM32L0X) && defined(LL_SYSCFG_EXTI_PORTH)
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/*
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* Ports F and G are not present on some STM32L0 parts, so
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* for these parts port H external interrupt should be enabled
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* by writing value 0x5 instead of 0x7.
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*/
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if (port == STM32_PORTH) {
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port = LL_SYSCFG_EXTI_PORTH;
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}
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#endif
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z_stm32_hsem_lock(CFG_HW_EXTI_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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LL_GPIO_AF_SetEXTISource(port, ll_line);
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti)
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LL_EXTI_SetEXTISource(port, ll_line);
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7rs_exti)
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LL_SBS_SetEXTISource(port, ll_line);
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#else
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LL_SYSCFG_SetEXTISource(port, ll_line);
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#endif
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z_stm32_hsem_unlock(CFG_HW_EXTI_SEMID);
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}
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uint32_t stm32_exti_get_line_src_port(gpio_pin_t line)
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{
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uint32_t ll_line = stm32_exti_linenum_to_src_cfg_line(line);
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uint32_t port;
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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port = LL_GPIO_AF_GetEXTISource(ll_line);
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti)
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port = LL_EXTI_GetEXTISource(ll_line);
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7rs_exti)
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port = LL_SBS_GetEXTISource(ll_line);
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#else
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port = LL_SYSCFG_GetEXTISource(ll_line);
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#endif
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#if defined(CONFIG_SOC_SERIES_STM32L0X) && defined(LL_SYSCFG_EXTI_PORTH)
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/*
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* Ports F and G are not present on some STM32L0 parts, so
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* for these parts port H external interrupt is enabled
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* by writing value 0x5 instead of 0x7.
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*/
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if (port == LL_SYSCFG_EXTI_PORTH) {
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port = STM32_PORTH;
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}
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#endif
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return port;
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}
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