458 lines
16 KiB
C
458 lines
16 KiB
C
/*
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* Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT xlnx_xps_gpio_1_00_a
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/irq.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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/* AXI GPIO v2 register offsets (See Xilinx PG144 for details) */
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#define GPIO_DATA_OFFSET 0x0000
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#define GPIO_TRI_OFFSET 0x0004
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#define GPIO2_OFFSET 0x0008
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#define GPIO2_DATA_OFFSET 0x0008
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#define GPIO2_TRI_OFFSET 0x000c
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#define GIER_OFFSET 0x011c
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#define IPISR_OFFSET 0x0120
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#define IPIER_OFFSET 0x0128
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/* GIER bit definitions */
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#define GIER_GIE BIT(31)
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/* IPISR and IPIER bit definitions */
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#define IPIXX_CH1_IE BIT(0)
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#define IPIXX_CH2_IE BIT(1)
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/* Maximum number of GPIOs supported per channel */
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#define MAX_GPIOS 32
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struct gpio_xlnx_axi_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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mm_reg_t base;
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uint8_t channel;
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bool all_inputs: 1;
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bool all_outputs: 1;
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bool interrupts_available: 1;
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
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void (*irq_config_func)(const struct device *dev);
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#endif
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};
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struct gpio_xlnx_axi_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* Shadow registers for data out and tristate */
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uint32_t dout;
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uint32_t tri;
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
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uint32_t previous_data_reading;
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sys_slist_t callbacks;
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uint32_t rising_edge_interrupts;
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uint32_t falling_edge_interrupts;
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/* Workaround to handle channel 2 interrupts from channel 1*/
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const struct device *other_channel_device;
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#endif
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};
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static inline uint32_t gpio_xlnx_axi_read_data(const struct device *dev)
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{
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const struct gpio_xlnx_axi_config *config = dev->config;
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return sys_read32(config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET);
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}
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static inline void gpio_xlnx_axi_write_data(const struct device *dev, uint32_t val)
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{
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const struct gpio_xlnx_axi_config *config = dev->config;
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sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET);
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}
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static inline void gpio_xlnx_axi_write_tri(const struct device *dev, uint32_t val)
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{
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const struct gpio_xlnx_axi_config *config = dev->config;
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sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_TRI_OFFSET);
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}
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static int gpio_xlnx_axi_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_xlnx_axi_config *config = dev->config;
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struct gpio_xlnx_axi_data *data = dev->data;
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unsigned int key;
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if (!(BIT(pin) & config->common.port_pin_mask)) {
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return -EINVAL;
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}
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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return -ENOTSUP;
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}
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if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
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return -ENOTSUP;
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}
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if (((flags & GPIO_INPUT) != 0) && config->all_outputs) {
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return -ENOTSUP;
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}
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if (((flags & GPIO_OUTPUT) != 0) && config->all_inputs) {
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return -ENOTSUP;
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}
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key = irq_lock();
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switch (flags & GPIO_DIR_MASK) {
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case GPIO_INPUT:
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data->tri |= BIT(pin);
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break;
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case GPIO_OUTPUT:
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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data->dout |= BIT(pin);
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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data->dout &= ~BIT(pin);
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}
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data->tri &= ~BIT(pin);
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break;
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default:
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return -ENOTSUP;
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}
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gpio_xlnx_axi_write_data(dev, data->dout);
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gpio_xlnx_axi_write_tri(dev, data->tri);
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irq_unlock(key);
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return 0;
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}
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static int gpio_xlnx_axi_port_get_raw(const struct device *dev, gpio_port_value_t *value)
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{
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*value = gpio_xlnx_axi_read_data(dev);
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return 0;
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}
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static int gpio_xlnx_axi_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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struct gpio_xlnx_axi_data *data = dev->data;
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unsigned int key;
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key = irq_lock();
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data->dout = (data->dout & ~mask) | (mask & value);
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gpio_xlnx_axi_write_data(dev, data->dout);
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irq_unlock(key);
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return 0;
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}
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static int gpio_xlnx_axi_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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struct gpio_xlnx_axi_data *data = dev->data;
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unsigned int key;
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key = irq_lock();
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data->dout |= pins;
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gpio_xlnx_axi_write_data(dev, data->dout);
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irq_unlock(key);
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return 0;
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}
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static int gpio_xlnx_axi_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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struct gpio_xlnx_axi_data *data = dev->data;
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unsigned int key;
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key = irq_lock();
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data->dout &= ~pins;
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gpio_xlnx_axi_write_data(dev, data->dout);
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irq_unlock(key);
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return 0;
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}
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static int gpio_xlnx_axi_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
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{
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struct gpio_xlnx_axi_data *data = dev->data;
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unsigned int key;
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key = irq_lock();
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data->dout ^= pins;
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gpio_xlnx_axi_write_data(dev, data->dout);
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irq_unlock(key);
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return 0;
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}
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
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/**
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* Enables interrupts for the given pins on the channel
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* The axi gpio can only enable interrupts for an entire port, so we need to track
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* the pins and modes ourselves.
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*/
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static int gpio_xlnx_axi_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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const struct gpio_xlnx_axi_config *config = dev->config;
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struct gpio_xlnx_axi_data *data = dev->data;
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const uint32_t pin_mask = BIT(pin);
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const uint32_t chan_mask = BIT(config->channel);
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unsigned int key;
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uint32_t enabled_interrupts;
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if (!config->interrupts_available) {
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return -ENOTSUP;
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}
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if ((mode & GPIO_INT_ENABLE) && !(mode & GPIO_INT_EDGE)) {
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/* only edge detection is supported */
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return -ENOTSUP;
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}
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key = irq_lock();
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data->rising_edge_interrupts &= ~pin_mask;
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data->falling_edge_interrupts &= ~pin_mask;
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if (mode & GPIO_INT_ENABLE) {
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if (trig & GPIO_INT_HIGH_1) {
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data->rising_edge_interrupts |= pin_mask;
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}
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if (trig & GPIO_INT_LOW_0) {
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data->falling_edge_interrupts |= pin_mask;
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}
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}
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/* if there's at least one pin interrupt enabled on the channel, enable the interrupts
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* for that entire channel without changing the other channel
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*/
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enabled_interrupts = sys_read32(config->base + IPIER_OFFSET);
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if (data->rising_edge_interrupts || data->falling_edge_interrupts) {
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if (!(enabled_interrupts & chan_mask)) {
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/* Clear any pending interrupts and update last state before enabling
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* interrupt
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*/
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if (sys_read32(config->base + IPISR_OFFSET) & chan_mask) {
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sys_write32(chan_mask, config->base + IPISR_OFFSET);
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}
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data->previous_data_reading = gpio_xlnx_axi_read_data(dev);
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enabled_interrupts |= chan_mask;
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}
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} else {
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enabled_interrupts &= ~chan_mask;
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}
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sys_write32(enabled_interrupts, config->base + IPIER_OFFSET);
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irq_unlock(key);
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return 0;
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}
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#endif
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
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static int gpio_xlnx_axi_manage_callback(const struct device *dev, struct gpio_callback *callback,
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bool set)
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{
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struct gpio_xlnx_axi_data *data = dev->data;
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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#endif
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
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/**
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* Returns the pins on this devices channel which changed and also have an interrupt enabled on that
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* pin. Also clears the pending interrupt for that channel.
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*/
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static uint32_t gpio_xlnx_axi_get_pending_int(const struct device *dev)
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{
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const struct gpio_xlnx_axi_config *config = dev->config;
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struct gpio_xlnx_axi_data *data = dev->data;
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const uint32_t chan_mask = BIT(config->channel);
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unsigned int key;
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uint32_t interrupt_flags;
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uint32_t current_data;
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uint32_t changed_pins;
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uint32_t changed_and_rising_edge;
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uint32_t changed_and_falling_edge;
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uint32_t interrupts;
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key = irq_lock();
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/* make sure interrupt was for this channel */
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interrupt_flags = sys_read32(config->base + IPISR_OFFSET);
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if (!(interrupt_flags & chan_mask)) {
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irq_unlock(key);
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return 0;
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}
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/* clear pending interrupt for the whole channel */
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sys_write32(chan_mask, config->base + IPISR_OFFSET);
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/* find which pins changed and also have an interrupt enabled */
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current_data = gpio_xlnx_axi_read_data(dev);
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changed_pins = current_data ^ data->previous_data_reading;
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data->previous_data_reading = current_data;
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changed_and_rising_edge = (changed_pins & current_data);
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changed_and_falling_edge = (changed_pins & ~current_data);
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interrupts = (changed_and_rising_edge & data->rising_edge_interrupts) |
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(changed_and_falling_edge & data->falling_edge_interrupts);
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irq_unlock(key);
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return interrupts;
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}
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#endif
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
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static void gpio_xlnx_axi_isr(const struct device *dev)
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{
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struct gpio_xlnx_axi_data *data = dev->data;
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gpio_fire_callbacks(&data->callbacks, dev, gpio_xlnx_axi_get_pending_int(dev));
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/* Since both channels use the same interrupt, only the first channel registers the ISR.
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* If the second channel is also enabled, then check for any events on it as well.
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*/
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if (data->other_channel_device) {
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struct gpio_xlnx_axi_data *other_data = data->other_channel_device->data;
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gpio_fire_callbacks(&other_data->callbacks, data->other_channel_device,
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gpio_xlnx_axi_get_pending_int(data->other_channel_device));
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}
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}
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#endif
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static int gpio_xlnx_axi_init(const struct device *dev)
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{
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struct gpio_xlnx_axi_data *data = dev->data;
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gpio_xlnx_axi_write_data(dev, data->dout);
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gpio_xlnx_axi_write_tri(dev, data->tri);
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
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const struct gpio_xlnx_axi_config *config = dev->config;
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if (config->irq_config_func != NULL) {
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/* Note: This is only called for the first channel, even if the second is enabled.
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* Need to perform the setup for both channels.
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* Disable all interrupts.
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*/
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sys_write32(0x0, config->base + IPIER_OFFSET);
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/* Clear all pending interrupts */
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sys_write32(sys_read32(config->base + IPISR_OFFSET), config->base + IPISR_OFFSET);
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/* Enable global interrupts for this gpio device */
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sys_write32(GIER_GIE, config->base + GIER_OFFSET);
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config->irq_config_func(dev);
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}
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#endif
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return 0;
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}
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static const struct gpio_driver_api gpio_xlnx_axi_driver_api = {
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.pin_configure = gpio_xlnx_axi_pin_configure,
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.port_get_raw = gpio_xlnx_axi_port_get_raw,
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.port_set_masked_raw = gpio_xlnx_axi_port_set_masked_raw,
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.port_set_bits_raw = gpio_xlnx_axi_port_set_bits_raw,
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.port_clear_bits_raw = gpio_xlnx_axi_port_clear_bits_raw,
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.port_toggle_bits = gpio_xlnx_axi_port_toggle_bits,
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
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.pin_interrupt_configure = gpio_xlnx_axi_pin_interrupt_configure,
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.manage_callback = gpio_xlnx_axi_manage_callback,
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.get_pending_int = gpio_xlnx_axi_get_pending_int,
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#endif
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};
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#define GPIO_XLNX_AXI_GPIO2_HAS_COMPAT_STATUS_OKAY(n) \
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UTIL_AND(DT_NODE_HAS_COMPAT(DT_INST_CHILD(n, gpio2), xlnx_xps_gpio_1_00_a_gpio2), \
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DT_NODE_HAS_STATUS_OKAY(DT_INST_CHILD(n, gpio2)))
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#define GPIO_XLNX_AXI_GPIO2_COND_INIT(n) \
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IF_ENABLED(UTIL_AND(DT_INST_PROP_OR(n, xlnx_is_dual, 1), \
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GPIO_XLNX_AXI_GPIO2_HAS_COMPAT_STATUS_OKAY(n)), \
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(GPIO_XLNX_AXI_GPIO2_INIT(n)));
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#define GPIO_XLNX_AXI_GPIO2_INIT(n) \
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static struct gpio_xlnx_axi_data gpio_xlnx_axi_##n##_2_data = { \
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.dout = DT_INST_PROP_OR(n, xlnx_dout_default_2, 0), \
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.tri = DT_INST_PROP_OR(n, xlnx_tri_default_2, GENMASK(MAX_GPIOS - 1, 0)), \
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}; \
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\
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static const struct gpio_xlnx_axi_config gpio_xlnx_axi_##n##_2_config = { \
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.common = \
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{ \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS( \
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DT_INST_PROP_OR(n, xlnx_gpio2_width, MAX_GPIOS)), \
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}, \
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.base = DT_INST_REG_ADDR(n), \
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.channel = 1, \
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.all_inputs = DT_INST_PROP_OR(n, xlnx_all_inputs_2, 0), \
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.all_outputs = DT_INST_PROP_OR(n, xlnx_all_outputs_2, 0), \
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.interrupts_available = DT_INST_NODE_HAS_PROP(n, interrupts)}; \
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\
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DEVICE_DT_DEFINE(DT_INST_CHILD(n, gpio2), &gpio_xlnx_axi_init, NULL, \
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&gpio_xlnx_axi_##n##_2_data, &gpio_xlnx_axi_##n##_2_config, PRE_KERNEL_1, \
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CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_axi_driver_api);
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#define GPIO_XLNX_AXI_INIT(n) \
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IF_ENABLED(DT_INST_NODE_HAS_PROP(n, interrupts), \
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(static void gpio_xlnx_axi_##n##_irq_config(const struct device *dev);)) \
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\
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GPIO_XLNX_AXI_GPIO2_COND_INIT(n); \
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\
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static struct gpio_xlnx_axi_data gpio_xlnx_axi_##n##_data = { \
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.dout = DT_INST_PROP_OR(n, xlnx_dout_default, 0), \
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.tri = DT_INST_PROP_OR(n, xlnx_tri_default, GENMASK(MAX_GPIOS - 1, 0)), \
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IF_ENABLED(UTIL_AND(UTIL_AND(DT_INST_NODE_HAS_PROP(n, interrupts), \
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DT_INST_PROP_OR(n, xlnx_is_dual, 1)), \
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GPIO_XLNX_AXI_GPIO2_HAS_COMPAT_STATUS_OKAY(n)), \
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(.other_channel_device = DEVICE_DT_GET(DT_INST_CHILD(n, gpio2))))}; \
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\
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static const struct gpio_xlnx_axi_config gpio_xlnx_axi_##n##_config = { \
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.common = \
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{ \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS( \
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DT_INST_PROP_OR(n, xlnx_gpio_width, MAX_GPIOS)), \
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}, \
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.base = DT_INST_REG_ADDR(n), \
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.channel = 0, \
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.all_inputs = DT_INST_PROP_OR(n, xlnx_all_inputs, 0), \
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.all_outputs = DT_INST_PROP_OR(n, xlnx_all_outputs, 0), \
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.interrupts_available = DT_INST_NODE_HAS_PROP(n, interrupts), \
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IF_ENABLED(DT_INST_NODE_HAS_PROP(n, interrupts), \
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(.irq_config_func = gpio_xlnx_axi_##n##_irq_config))}; \
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\
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IF_ENABLED(DT_INST_NODE_HAS_PROP(n, interrupts), \
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(static void gpio_xlnx_axi_##n##_irq_config(const struct device *dev) \
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{ \
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ARG_UNUSED(dev); \
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\
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
|
|
gpio_xlnx_axi_isr, DEVICE_DT_INST_GET(n), 0); \
|
|
\
|
|
irq_enable(DT_INST_IRQN(n)); \
|
|
})) \
|
|
\
|
|
DEVICE_DT_INST_DEFINE(n, gpio_xlnx_axi_init, NULL, &gpio_xlnx_axi_##n##_data, \
|
|
&gpio_xlnx_axi_##n##_config, PRE_KERNEL_1, \
|
|
CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_axi_driver_api);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(GPIO_XLNX_AXI_INIT)
|