297 lines
8.0 KiB
C
297 lines
8.0 KiB
C
/*
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* Copyright (c) 2018 Zilogic Systems.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_stellaris_gpio
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#include <errno.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/irq.h>
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#include <soc.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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typedef void (*config_func_t)(const struct device *dev);
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struct gpio_stellaris_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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uint32_t base;
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uint32_t port_map;
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config_func_t config_func;
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};
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struct gpio_stellaris_runtime {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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sys_slist_t cb;
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};
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#define GPIO_REG_ADDR(base, offset) (base + offset)
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#define GPIO_RW_ADDR(base, offset, p) \
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(GPIO_REG_ADDR(base, offset) | (1 << (p + 2)))
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#define GPIO_RW_MASK_ADDR(base, offset, mask) \
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(GPIO_REG_ADDR(base, offset) | (mask << 2))
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enum gpio_regs {
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GPIO_DATA_OFFSET = 0x000,
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GPIO_DIR_OFFSET = 0x400,
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GPIO_DEN_OFFSET = 0x51C,
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GPIO_IS_OFFSET = 0x404,
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GPIO_IBE_OFFSET = 0x408,
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GPIO_IEV_OFFSET = 0x40C,
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GPIO_IM_OFFSET = 0x410,
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GPIO_MIS_OFFSET = 0x418,
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GPIO_ICR_OFFSET = 0x41C,
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};
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static void gpio_stellaris_isr(const struct device *dev)
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{
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const struct gpio_stellaris_config * const cfg = dev->config;
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struct gpio_stellaris_runtime *context = dev->data;
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uint32_t base = cfg->base;
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uint32_t int_stat = sys_read32(GPIO_REG_ADDR(base, GPIO_MIS_OFFSET));
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gpio_fire_callbacks(&context->cb, dev, int_stat);
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sys_write32(int_stat, GPIO_REG_ADDR(base, GPIO_ICR_OFFSET));
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}
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static int gpio_stellaris_configure(const struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_stellaris_config *cfg = dev->config;
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uint32_t base = cfg->base;
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uint32_t port_map = cfg->port_map;
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if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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return -ENOTSUP;
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}
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/* Check for pin availability */
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if (!sys_test_bit((uint32_t)&port_map, pin)) {
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return -EINVAL;
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}
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if ((flags & GPIO_OUTPUT) != 0) {
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mm_reg_t mask_addr;
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mask_addr = GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, BIT(pin));
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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sys_write32(BIT(pin), mask_addr);
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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sys_write32(0, mask_addr);
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}
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sys_set_bit(GPIO_REG_ADDR(base, GPIO_DIR_OFFSET), pin);
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/* Pin digital enable */
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sys_set_bit(GPIO_REG_ADDR(base, GPIO_DEN_OFFSET), pin);
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} else if ((flags & GPIO_INPUT) != 0) {
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sys_clear_bit(GPIO_REG_ADDR(base, GPIO_DIR_OFFSET), pin);
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/* Pin digital enable */
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sys_set_bit(GPIO_REG_ADDR(base, GPIO_DEN_OFFSET), pin);
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} else {
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/* Pin digital disable */
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sys_clear_bit(GPIO_REG_ADDR(base, GPIO_DEN_OFFSET), pin);
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}
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return 0;
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}
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#ifdef CONFIG_GPIO_GET_CONFIG
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static int gpio_stellaris_get_config(const struct device *dev,
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gpio_pin_t pin,
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gpio_flags_t *out_flags)
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{
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const struct gpio_stellaris_config *cfg = dev->config;
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uint32_t base = cfg->base;
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gpio_flags_t flags = 0;
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mm_reg_t mask_addr;
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if (sys_test_bit(GPIO_REG_ADDR(base, GPIO_DEN_OFFSET), pin) == 0) {
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flags = GPIO_DISCONNECTED;
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} else if (sys_test_bit(GPIO_REG_ADDR(base, GPIO_DIR_OFFSET), pin)) {
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mask_addr = GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, BIT(pin));
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if (sys_test_bit(mask_addr, pin)) {
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flags |= GPIO_OUTPUT_HIGH;
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} else {
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flags |= GPIO_OUTPUT_LOW;
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}
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} else {
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flags = GPIO_INPUT;
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}
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*out_flags = flags;
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return 0;
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}
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#endif
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static int gpio_stellaris_port_get_raw(const struct device *dev,
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uint32_t *value)
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{
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const struct gpio_stellaris_config *cfg = dev->config;
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uint32_t base = cfg->base;
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*value = sys_read32(GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, 0xff));
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return 0;
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}
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static int gpio_stellaris_port_set_masked_raw(const struct device *dev,
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uint32_t mask,
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uint32_t value)
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{
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const struct gpio_stellaris_config *cfg = dev->config;
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uint32_t base = cfg->base;
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sys_write32(value, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, mask));
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return 0;
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}
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static int gpio_stellaris_port_set_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_stellaris_config *cfg = dev->config;
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uint32_t base = cfg->base;
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sys_write32(mask, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, mask));
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return 0;
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}
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static int gpio_stellaris_port_clear_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_stellaris_config *cfg = dev->config;
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uint32_t base = cfg->base;
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sys_write32(0, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, mask));
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return 0;
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}
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static int gpio_stellaris_port_toggle_bits(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_stellaris_config *cfg = dev->config;
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uint32_t base = cfg->base;
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uint32_t value;
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value = sys_read32(GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, 0xff));
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value ^= mask;
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sys_write32(value, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, 0xff));
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return 0;
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}
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static int gpio_stellaris_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_stellaris_config *cfg = dev->config;
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uint32_t base = cfg->base;
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/* Check if GPIO port needs interrupt support */
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if (mode == GPIO_INT_MODE_DISABLED) {
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/* Set the mask to disable the interrupt */
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sys_set_bit(GPIO_REG_ADDR(base, GPIO_IM_OFFSET), pin);
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} else {
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if (mode == GPIO_INT_MODE_EDGE) {
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sys_clear_bit(GPIO_REG_ADDR(base, GPIO_IS_OFFSET), pin);
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} else {
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sys_set_bit(GPIO_REG_ADDR(base, GPIO_IS_OFFSET), pin);
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}
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if (trig == GPIO_INT_TRIG_BOTH) {
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sys_set_bit(GPIO_REG_ADDR(base, GPIO_IBE_OFFSET), pin);
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} else if (trig == GPIO_INT_TRIG_HIGH) {
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sys_set_bit(GPIO_REG_ADDR(base, GPIO_IEV_OFFSET), pin);
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} else {
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sys_clear_bit(GPIO_REG_ADDR(base,
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GPIO_IEV_OFFSET), pin);
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}
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/* Clear the Mask to enable the interrupt */
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sys_clear_bit(GPIO_REG_ADDR(base, GPIO_IM_OFFSET), pin);
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}
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return 0;
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}
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static int gpio_stellaris_init(const struct device *dev)
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{
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const struct gpio_stellaris_config *cfg = dev->config;
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cfg->config_func(dev);
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return 0;
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}
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static int gpio_stellaris_manage_callback(const struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_stellaris_runtime *context = dev->data;
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gpio_manage_callback(&context->cb, callback, set);
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return 0;
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}
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static const struct gpio_driver_api gpio_stellaris_driver_api = {
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.pin_configure = gpio_stellaris_configure,
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#ifdef CONFIG_GPIO_GET_CONFIG
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.pin_get_config = gpio_stellaris_get_config,
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#endif
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.port_get_raw = gpio_stellaris_port_get_raw,
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.port_set_masked_raw = gpio_stellaris_port_set_masked_raw,
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.port_set_bits_raw = gpio_stellaris_port_set_bits_raw,
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.port_clear_bits_raw = gpio_stellaris_port_clear_bits_raw,
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.port_toggle_bits = gpio_stellaris_port_toggle_bits,
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.pin_interrupt_configure = gpio_stellaris_pin_interrupt_configure,
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.manage_callback = gpio_stellaris_manage_callback,
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};
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#define STELLARIS_GPIO_DEVICE(n) \
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static void port_## n ##_stellaris_config_func(const struct device *dev); \
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\
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static struct gpio_stellaris_runtime port_## n ##_stellaris_runtime; \
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\
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static const struct gpio_stellaris_config gpio_stellaris_port_## n ##_config = {\
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.base = DT_INST_REG_ADDR(n), \
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.port_map = BIT_MASK(DT_INST_PROP(n, ngpios)), \
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.config_func = port_## n ##_stellaris_config_func, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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gpio_stellaris_init, \
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NULL, \
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&port_## n ##_stellaris_runtime, \
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&gpio_stellaris_port_## n ##_config, \
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POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_stellaris_driver_api); \
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\
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static void port_## n ##_stellaris_config_func(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), \
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DT_INST_IRQ(n, priority), \
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gpio_stellaris_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQN(n)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(STELLARIS_GPIO_DEVICE)
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