278 lines
7.1 KiB
C
278 lines
7.1 KiB
C
/*
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* Copyright (c) 2018 Justin Watson
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* Copyright (c) 2020 ATL Electronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT cypress_psoc6_gpio
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include "cy_gpio.h"
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#include "cy_sysint.h"
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#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(gpio_psoc6);
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typedef void (*config_func_t)(const struct device *dev);
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struct gpio_psoc6_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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GPIO_PRT_Type *regs;
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config_func_t config_func;
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};
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struct gpio_psoc6_runtime {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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sys_slist_t cb;
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};
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static int gpio_psoc6_config(const struct device *dev,
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gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_psoc6_config * const cfg = dev->config;
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GPIO_PRT_Type * const port = cfg->regs;
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uint32_t drv_mode;
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uint32_t pin_val;
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if (flags & GPIO_OUTPUT) {
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if (flags & GPIO_SINGLE_ENDED) {
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drv_mode = (flags & GPIO_LINE_OPEN_DRAIN) ?
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CY_GPIO_DM_OD_DRIVESLOW_IN_OFF :
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CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF;
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pin_val = (flags & GPIO_LINE_OPEN_DRAIN) ? 1 : 0;
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} else {
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drv_mode = CY_GPIO_DM_STRONG_IN_OFF;
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pin_val = (flags & GPIO_OUTPUT_INIT_HIGH) ? 1 : 0;
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}
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} else {
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if ((flags & GPIO_PULL_UP) && (flags & GPIO_PULL_DOWN)) {
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drv_mode = CY_GPIO_DM_PULLUP_DOWN_IN_OFF;
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} else if (flags & GPIO_PULL_UP) {
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drv_mode = CY_GPIO_DM_PULLUP_IN_OFF;
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} else if (flags & GPIO_PULL_DOWN) {
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drv_mode = CY_GPIO_DM_PULLDOWN_IN_OFF;
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} else {
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drv_mode = CY_GPIO_DM_ANALOG;
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}
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pin_val = (flags & GPIO_PULL_UP) ? 1 : 0;
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}
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if (flags & GPIO_INPUT) {
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/* enable input buffer */
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drv_mode |= CY_GPIO_DM_HIGHZ;
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}
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Cy_GPIO_Pin_FastInit(port, pin, drv_mode, pin_val, HSIOM_SEL_GPIO);
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Cy_GPIO_SetVtrip(port, pin, CY_GPIO_VTRIP_CMOS);
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Cy_GPIO_SetSlewRate(port, pin, CY_GPIO_SLEW_FAST);
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Cy_GPIO_SetDriveSel(port, pin, CY_GPIO_DRIVE_FULL);
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LOG_DBG("P: 0x%08x, Pin: %d, Mode: 0x%08x, Val: 0x%02x",
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(unsigned int) port, pin, drv_mode, pin_val);
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return 0;
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}
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static int gpio_psoc6_port_get_raw(const struct device *dev,
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uint32_t *value)
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{
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const struct gpio_psoc6_config * const cfg = dev->config;
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GPIO_PRT_Type * const port = cfg->regs;
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*value = GPIO_PRT_IN(port);
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LOG_DBG("P: 0x%08x, V: 0x%08x", (unsigned int) port, *value);
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return 0;
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}
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static int gpio_psoc6_port_set_masked_raw(const struct device *dev,
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uint32_t mask,
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uint32_t value)
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{
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const struct gpio_psoc6_config * const cfg = dev->config;
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GPIO_PRT_Type * const port = cfg->regs;
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GPIO_PRT_OUT(port) = (GPIO_PRT_IN(port) & ~mask) | (mask & value);
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return 0;
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}
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static int gpio_psoc6_port_set_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_psoc6_config * const cfg = dev->config;
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GPIO_PRT_Type * const port = cfg->regs;
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GPIO_PRT_OUT_SET(port) = mask;
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return 0;
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}
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static int gpio_psoc6_port_clear_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_psoc6_config * const cfg = dev->config;
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GPIO_PRT_Type * const port = cfg->regs;
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GPIO_PRT_OUT_CLR(port) = mask;
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return 0;
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}
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static int gpio_psoc6_port_toggle_bits(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_psoc6_config * const cfg = dev->config;
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GPIO_PRT_Type * const port = cfg->regs;
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GPIO_PRT_OUT_INV(port) = mask;
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return 0;
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}
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static int gpio_psoc6_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_psoc6_config * const cfg = dev->config;
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GPIO_PRT_Type * const port = cfg->regs;
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uint32_t is_enabled = ((mode == GPIO_INT_MODE_DISABLED) ? 0 : 1);
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uint32_t lv_trg = CY_GPIO_INTR_DISABLE;
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if (mode == GPIO_INT_MODE_LEVEL) {
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return -ENOTSUP;
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}
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if (is_enabled) {
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switch (trig) {
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case GPIO_INT_TRIG_BOTH:
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lv_trg = CY_GPIO_INTR_BOTH;
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break;
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case GPIO_INT_TRIG_HIGH:
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lv_trg = CY_GPIO_INTR_RISING;
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break;
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case GPIO_INT_TRIG_LOW:
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lv_trg = CY_GPIO_INTR_FALLING;
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break;
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default:
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return -EINVAL;
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}
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}
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Cy_GPIO_ClearInterrupt(port, pin);
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Cy_GPIO_SetInterruptEdge(port, pin, lv_trg);
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Cy_GPIO_SetInterruptMask(port, pin, is_enabled);
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/**
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* The driver will set 50ns glitch free filter for any interrupt.
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*/
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Cy_GPIO_SetFilter(port, pin);
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LOG_DBG("config: Pin: %d, Trg: %d", pin, lv_trg);
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return 0;
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}
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static void gpio_psoc6_isr(const struct device *dev)
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{
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const struct gpio_psoc6_config * const cfg = dev->config;
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GPIO_PRT_Type * const port = cfg->regs;
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struct gpio_psoc6_runtime *context = dev->data;
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uint32_t int_stat;
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int_stat = GPIO_PRT_INTR_MASKED(port);
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/* Any INTR MMIO registers AHB clearing must be preceded with an AHB
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* read access. Taken from Cy_GPIO_ClearInterrupt()
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*/
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(void)GPIO_PRT_INTR(port);
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GPIO_PRT_INTR(port) = int_stat;
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/* This read ensures that the initial write has been flushed out to HW
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*/
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(void)GPIO_PRT_INTR(port);
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gpio_fire_callbacks(&context->cb, dev, int_stat);
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}
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static int gpio_psoc6_manage_callback(const struct device *port,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_psoc6_runtime *context = port->data;
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return gpio_manage_callback(&context->cb, callback, set);
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}
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static uint32_t gpio_psoc6_get_pending_int(const struct device *dev)
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{
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const struct gpio_psoc6_config * const cfg = dev->config;
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GPIO_PRT_Type * const port = cfg->regs;
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LOG_DBG("Pending: 0x%08x", GPIO_PRT_INTR_MASKED(port));
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return GPIO_PRT_INTR_MASKED(port);
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}
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static const struct gpio_driver_api gpio_psoc6_api = {
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.pin_configure = gpio_psoc6_config,
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.port_get_raw = gpio_psoc6_port_get_raw,
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.port_set_masked_raw = gpio_psoc6_port_set_masked_raw,
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.port_set_bits_raw = gpio_psoc6_port_set_bits_raw,
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.port_clear_bits_raw = gpio_psoc6_port_clear_bits_raw,
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.port_toggle_bits = gpio_psoc6_port_toggle_bits,
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.pin_interrupt_configure = gpio_psoc6_pin_interrupt_configure,
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.manage_callback = gpio_psoc6_manage_callback,
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.get_pending_int = gpio_psoc6_get_pending_int,
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};
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int gpio_psoc6_init(const struct device *dev)
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{
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const struct gpio_psoc6_config * const cfg = dev->config;
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cfg->config_func(dev);
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return 0;
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}
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#define GPIO_PSOC6_INIT(n) \
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static void port_##n##_psoc6_config_func(const struct device *dev); \
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\
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static const struct gpio_psoc6_config port_##n##_psoc6_config = { \
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
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}, \
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.regs = (GPIO_PRT_Type *)DT_INST_REG_ADDR(n), \
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.config_func = port_##n##_psoc6_config_func, \
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}; \
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\
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static struct gpio_psoc6_runtime port_##n##_psoc6_runtime = { 0 }; \
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\
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DEVICE_DT_INST_DEFINE(n, gpio_psoc6_init, NULL, \
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&port_##n##_psoc6_runtime, \
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&port_##n##_psoc6_config, PRE_KERNEL_1, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_psoc6_api); \
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\
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static void port_##n##_psoc6_config_func(const struct device *dev) \
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{ \
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CY_PSOC6_DT_INST_NVIC_INSTALL(n, gpio_psoc6_isr); \
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};
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DT_INST_FOREACH_STATUS_OKAY(GPIO_PSOC6_INIT)
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