483 lines
13 KiB
C
483 lines
13 KiB
C
/*
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* Copyright 2017-2020,2022-2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_lpc_gpio_port
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/** @file
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* @brief GPIO driver for LPC54XXX family
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*
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* Note:
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* - fsl_pint internally tries to manage interrupts, but this is not used (e.g.
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* s_pintCallback), Zephyr's interrupt management system is used in place.
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*/
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/irq.h>
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#include <soc.h>
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#include <fsl_common.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#ifdef CONFIG_NXP_PINT
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#include <zephyr/drivers/interrupt_controller/nxp_pint.h>
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#endif
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#include <fsl_gpio.h>
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#include <fsl_device_registers.h>
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#ifdef MCI_IO_MUX
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#include <zephyr/drivers/pinctrl.h>
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#endif
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/* Interrupt sources, matching int-source enum in DTS binding definition */
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#define INT_SOURCE_PINT 0
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#define INT_SOURCE_INTA 1
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#define INT_SOURCE_INTB 2
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#define INT_SOURCE_NONE 3
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struct gpio_mcux_lpc_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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GPIO_Type *gpio_base;
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uint8_t int_source;
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#ifdef IOPCTL
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IOPCTL_Type *pinmux_base;
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#endif
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#ifdef IOCON
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IOCON_Type *pinmux_base;
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#endif
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#ifdef MCI_IO_MUX
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MCI_IO_MUX_Type * pinmux_base;
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#endif
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uint32_t port_no;
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};
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struct gpio_mcux_lpc_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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};
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static int gpio_mcux_lpc_configure(const struct device *dev, gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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uint32_t port = config->port_no;
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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#ifdef IOPCTL /* RT600 and RT500 series */
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IOPCTL_Type *pinmux_base = config->pinmux_base;
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volatile uint32_t *pinconfig = (volatile uint32_t *)&(pinmux_base->PIO[port][pin]);
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/*
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* Enable input buffer for both input and output pins, it costs
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* nothing and allows values to be read back.
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*/
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*pinconfig |= IOPCTL_PIO_INBUF_EN;
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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*pinconfig |= IOPCTL_PIO_PSEDRAIN_EN;
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} else {
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*pinconfig &= ~IOPCTL_PIO_PSEDRAIN_EN;
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}
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/* Select GPIO mux for this pin (func 0 is always GPIO) */
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*pinconfig &= ~(IOPCTL_PIO_FSEL_MASK);
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#endif
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#ifdef IOCON /* LPC SOCs */
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volatile uint32_t *pinconfig;
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IOCON_Type *pinmux_base;
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pinmux_base = config->pinmux_base;
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pinconfig = (volatile uint32_t *)&(pinmux_base->PIO[port][pin]);
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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/* Set ODE bit. */
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*pinconfig |= IOCON_PIO_OD_MASK;
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}
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if ((flags & GPIO_INPUT) != 0) {
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/* Set DIGIMODE bit */
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*pinconfig |= IOCON_PIO_DIGIMODE_MASK;
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}
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/* Select GPIO mux for this pin (func 0 is always GPIO) */
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*pinconfig &= ~(IOCON_PIO_FUNC_MASK);
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#endif
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#ifdef MCI_IO_MUX /* RW61x SOCs */
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/* Construct a pin control state, and apply it directly. */
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pinctrl_soc_pin_t pin_cfg;
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if (config->port_no == 1) {
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pin_cfg = IOMUX_GPIO_IDX(pin + 32) | IOMUX_TYPE(IOMUX_GPIO);
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} else {
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pin_cfg = IOMUX_GPIO_IDX(pin) | IOMUX_TYPE(IOMUX_GPIO);
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}
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/* Add pull up flags, if required */
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if ((flags & GPIO_PULL_UP) != 0) {
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pin_cfg |= IOMUX_PAD_PULL(0x1);
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} else if ((flags & GPIO_PULL_DOWN) != 0) {
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pin_cfg |= IOMUX_PAD_PULL(0x2);
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}
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pinctrl_configure_pins(&pin_cfg, 1, 0);
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#endif
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if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) {
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#ifdef IOPCTL /* RT600 and RT500 series */
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*pinconfig |= IOPCTL_PIO_PUPD_EN;
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if ((flags & GPIO_PULL_UP) != 0) {
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*pinconfig |= IOPCTL_PIO_PULLUP_EN;
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} else if ((flags & GPIO_PULL_DOWN) != 0) {
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*pinconfig &= ~(IOPCTL_PIO_PULLUP_EN);
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}
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#endif
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#ifdef IOCON /* LPC SOCs */
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*pinconfig &= ~(IOCON_PIO_MODE_PULLUP|IOCON_PIO_MODE_PULLDOWN);
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if ((flags & GPIO_PULL_UP) != 0) {
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*pinconfig |= IOCON_PIO_MODE_PULLUP;
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} else if ((flags & GPIO_PULL_DOWN) != 0) {
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*pinconfig |= IOCON_PIO_MODE_PULLDOWN;
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}
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#endif
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} else {
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#ifdef IOPCTL /* RT600 and RT500 series */
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*pinconfig &= ~IOPCTL_PIO_PUPD_EN;
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#endif
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#ifdef IOCON /* LPC SOCs */
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*pinconfig &= ~(IOCON_PIO_MODE_PULLUP|IOCON_PIO_MODE_PULLDOWN);
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#endif
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#ifdef MCI_IO_MUX
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#endif
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}
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/* supports access by pin now,you can add access by port when needed */
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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gpio_base->SET[port] = BIT(pin);
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}
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if (flags & GPIO_OUTPUT_INIT_LOW) {
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gpio_base->CLR[port] = BIT(pin);
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}
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/* input-0,output-1 */
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WRITE_BIT(gpio_base->DIR[port], pin, flags & GPIO_OUTPUT);
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return 0;
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}
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static int gpio_mcux_lpc_port_get_raw(const struct device *dev,
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uint32_t *value)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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*value = gpio_base->PIN[config->port_no];
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return 0;
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}
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static int gpio_mcux_lpc_port_set_masked_raw(const struct device *dev,
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uint32_t mask,
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uint32_t value)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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uint32_t port = config->port_no;
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/* Writing 0 allows R+W, 1 disables the pin */
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gpio_base->MASK[port] = ~mask;
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gpio_base->MPIN[port] = value;
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/* Enable back the pins, user won't assume pins remain masked*/
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gpio_base->MASK[port] = 0U;
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return 0;
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}
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static int gpio_mcux_lpc_port_set_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->SET[config->port_no] = mask;
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return 0;
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}
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static int gpio_mcux_lpc_port_clear_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->CLR[config->port_no] = mask;
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return 0;
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}
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static int gpio_mcux_lpc_port_toggle_bits(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->NOT[config->port_no] = mask;
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return 0;
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}
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#ifdef CONFIG_NXP_PINT
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/* Called by PINT when pin interrupt fires */
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static void gpio_mcux_lpc_pint_cb(uint8_t pin, void *user)
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{
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const struct device *dev = user;
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const struct gpio_mcux_lpc_config *config = dev->config;
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struct gpio_mcux_lpc_data *data = dev->data;
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uint32_t gpio_pin;
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/* Subtract port number times 32 from pin number to get GPIO API
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* pin number.
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*/
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gpio_pin = pin - (config->port_no * 32);
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gpio_fire_callbacks(&data->callbacks, dev, BIT(gpio_pin));
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}
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/* Installs interrupt handler using PINT interrupt controller. */
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static int gpio_mcux_lpc_pint_interrupt_cfg(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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enum nxp_pint_trigger interrupt_mode = NXP_PINT_NONE;
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uint32_t port = config->port_no;
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int ret;
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switch (mode) {
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case GPIO_INT_MODE_DISABLED:
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nxp_pint_pin_disable((port * 32) + pin);
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return 0;
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case GPIO_INT_MODE_LEVEL:
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if (trig == GPIO_INT_TRIG_HIGH) {
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interrupt_mode = NXP_PINT_HIGH;
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} else if (trig == GPIO_INT_TRIG_LOW) {
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interrupt_mode = NXP_PINT_LOW;
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} else {
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return -ENOTSUP;
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}
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break;
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case GPIO_INT_MODE_EDGE:
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if (trig == GPIO_INT_TRIG_HIGH) {
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interrupt_mode = NXP_PINT_RISING;
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} else if (trig == GPIO_INT_TRIG_LOW) {
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interrupt_mode = NXP_PINT_FALLING;
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} else {
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interrupt_mode = NXP_PINT_BOTH;
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}
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break;
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default:
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return -ENOTSUP;
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}
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/* PINT treats GPIO pins as continuous. Each port has 32 pins */
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ret = nxp_pint_pin_enable((port * 32) + pin, interrupt_mode, (trig & GPIO_INT_WAKEUP));
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if (ret < 0) {
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return ret;
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}
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/* Install callback */
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return nxp_pint_pin_set_callback((port * 32) + pin,
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gpio_mcux_lpc_pint_cb,
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(struct device *)dev);
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}
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#endif /* CONFIG_NXP_PINT */
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#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)
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static int gpio_mcux_lpc_module_interrupt_cfg(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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gpio_interrupt_index_t int_idx;
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gpio_interrupt_config_t pin_config;
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if (config->int_source == INT_SOURCE_NONE) {
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return -ENOTSUP;
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}
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/* Route interrupt to source A or B based on interrupt source */
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int_idx = (config->int_source == INT_SOURCE_INTA) ?
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kGPIO_InterruptA : kGPIO_InterruptB;
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/* Disable interrupt if requested */
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if (mode == GPIO_INT_MODE_DISABLED) {
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GPIO_PinDisableInterrupt(config->gpio_base, config->port_no, pin, int_idx);
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return 0;
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}
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/* Set pin interrupt level */
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if (mode == GPIO_INT_MODE_LEVEL) {
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pin_config.mode = kGPIO_PinIntEnableLevel;
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} else if (mode == GPIO_INT_MODE_EDGE) {
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pin_config.mode = kGPIO_PinIntEnableEdge;
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} else {
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return -ENOTSUP;
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}
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/* Set pin interrupt trigger */
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if (trig == GPIO_INT_TRIG_HIGH) {
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pin_config.polarity = kGPIO_PinIntEnableHighOrRise;
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} else if (trig == GPIO_INT_TRIG_LOW) {
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pin_config.polarity = kGPIO_PinIntEnableLowOrFall;
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} else {
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return -ENOTSUP;
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}
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/* Enable interrupt with new configuration */
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GPIO_SetPinInterruptConfig(config->gpio_base, config->port_no, pin, &pin_config);
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GPIO_PinEnableInterrupt(config->gpio_base, config->port_no, pin, int_idx);
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return 0;
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}
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/* GPIO module interrupt handler */
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void gpio_mcux_lpc_module_isr(const struct device *dev)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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struct gpio_mcux_lpc_data *data = dev->data;
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uint32_t status;
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status = GPIO_PortGetInterruptStatus(config->gpio_base,
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config->port_no,
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config->int_source == INT_SOURCE_INTA ?
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kGPIO_InterruptA : kGPIO_InterruptB);
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GPIO_PortClearInterruptFlags(config->gpio_base,
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config->port_no,
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config->int_source == INT_SOURCE_INTA ?
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kGPIO_InterruptA : kGPIO_InterruptB,
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status);
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gpio_fire_callbacks(&data->callbacks, dev, status);
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}
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#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */
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static int gpio_mcux_lpc_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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uint32_t port = config->port_no;
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/* Ensure pin used as interrupt is set as input*/
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if ((mode & GPIO_INT_ENABLE) &&
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((gpio_base->DIR[port] & BIT(pin)) != 0)) {
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return -ENOTSUP;
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}
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#if defined(CONFIG_NXP_PINT)
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if (config->int_source == INT_SOURCE_PINT) {
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return gpio_mcux_lpc_pint_interrupt_cfg(dev, pin, mode, trig);
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}
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#endif /* CONFIG_NXP_PINT */
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#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)
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return gpio_mcux_lpc_module_interrupt_cfg(dev, pin, mode, trig);
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#else
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return -ENOTSUP;
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#endif
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}
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static int gpio_mcux_lpc_manage_cb(const struct device *port,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_mcux_lpc_data *data = port->data;
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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static int gpio_mcux_lpc_init(const struct device *dev)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_PortInit(config->gpio_base, config->port_no);
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return 0;
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}
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static const struct gpio_driver_api gpio_mcux_lpc_driver_api = {
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.pin_configure = gpio_mcux_lpc_configure,
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.port_get_raw = gpio_mcux_lpc_port_get_raw,
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.port_set_masked_raw = gpio_mcux_lpc_port_set_masked_raw,
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.port_set_bits_raw = gpio_mcux_lpc_port_set_bits_raw,
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.port_clear_bits_raw = gpio_mcux_lpc_port_clear_bits_raw,
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.port_toggle_bits = gpio_mcux_lpc_port_toggle_bits,
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.pin_interrupt_configure = gpio_mcux_lpc_pin_interrupt_configure,
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.manage_callback = gpio_mcux_lpc_manage_cb,
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};
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#ifdef IOPCTL
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#define PINMUX_BASE IOPCTL
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#endif
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#ifdef IOCON
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#define PINMUX_BASE IOCON
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#endif
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#ifdef MCI_IO_MUX
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#define PINMUX_BASE MCI_IO_MUX
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#endif
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#define GPIO_MCUX_LPC_MODULE_IRQ_CONNECT(inst) \
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do { \
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IRQ_CONNECT(DT_INST_IRQ(inst, irq), \
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DT_INST_IRQ(inst, priority), \
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gpio_mcux_lpc_module_isr, DEVICE_DT_INST_GET(inst), 0); \
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irq_enable(DT_INST_IRQ(inst, irq)); \
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} while (false)
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#define GPIO_MCUX_LPC_MODULE_IRQ(inst) \
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IF_ENABLED(DT_INST_IRQ_HAS_IDX(inst, 0), \
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(GPIO_MCUX_LPC_MODULE_IRQ_CONNECT(inst)))
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#define GPIO_MCUX_LPC(n) \
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static int lpc_gpio_init_##n(const struct device *dev); \
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\
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static const struct gpio_mcux_lpc_config gpio_mcux_lpc_config_##n = { \
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.gpio_base = (GPIO_Type *)DT_REG_ADDR(DT_INST_PARENT(n)), \
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.pinmux_base = PINMUX_BASE, \
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.int_source = DT_INST_ENUM_IDX(n, int_source), \
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.port_no = DT_INST_REG_ADDR(n) \
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}; \
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\
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static struct gpio_mcux_lpc_data gpio_mcux_lpc_data_##n; \
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\
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DEVICE_DT_INST_DEFINE(n, lpc_gpio_init_##n, NULL, \
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&gpio_mcux_lpc_data_##n, \
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&gpio_mcux_lpc_config_##n, PRE_KERNEL_1, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_mcux_lpc_driver_api); \
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\
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static int lpc_gpio_init_##n(const struct device *dev) \
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{ \
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gpio_mcux_lpc_init(dev); \
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GPIO_MCUX_LPC_MODULE_IRQ(n); \
|
|
\
|
|
return 0; \
|
|
}
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(GPIO_MCUX_LPC)
|