235 lines
6.4 KiB
C
235 lines
6.4 KiB
C
/*
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* Copyright (c) 2023 Efinix Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT efinix_sapphire_gpio
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <errno.h>
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#include <string.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/types.h>
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LOG_MODULE_REGISTER(gpio_efinix_sapphire);
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#define SUPPORTED_FLAGS \
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(GPIO_INPUT | GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH | \
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GPIO_ACTIVE_LOW | GPIO_ACTIVE_HIGH)
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#define GPIO_LOW 0
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#define GPIO_HIGH 1
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#define BSP_GPIO_INPUT 0x00
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#define BSP_GPIO_OUTPUT 0x04
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#define BSP_GPIO_OUTPUT_ENABLE 0x08
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#define BSP_GPIO_INTERRUPT_RISE_ENABLE 0x20
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#define BSP_GPIO_INTERRUPT_FALL_ENABLE 0x24
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#define BSP_GPIO_INTERRUPT_HIGH_ENABLE 0x28
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#define BSP_GPIO_INTERRUPT_LOW_ENABLE 0x2c
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/* efinix sapphire specific gpio config struct */
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struct gpio_efinix_sapphire_cfg {
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uint32_t base_addr;
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int n_gpios;
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struct gpio_driver_config common;
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};
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/* efinix sapphire specific gpio data struct */
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struct gpio_efinix_sapphire_data {
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struct gpio_driver_data common;
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const struct device *dev;
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sys_slist_t cb;
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};
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/* Device access pointer helpers */
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#define DEV_GPIO_CFG(dev) ((const struct gpio_efinix_sapphire_cfg *)(dev)->config)
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#define GPIO_OUTPUT_ADDR config->base_addr + BSP_GPIO_OUTPUT
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static inline void cfg_output_enable_bit(const struct gpio_efinix_sapphire_cfg *config,
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gpio_pin_t pin, uint32_t type)
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{
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#define GPIO_OUTPUT_ENABLE_ADDR config->base_addr + BSP_GPIO_OUTPUT_ENABLE
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uint32_t c_reg_val = sys_read32(GPIO_OUTPUT_ENABLE_ADDR);
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if (type == GPIO_INPUT) {
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sys_write32(c_reg_val &= ~pin, GPIO_OUTPUT_ENABLE_ADDR);
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} else if (type == GPIO_OUTPUT) {
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sys_write32(c_reg_val |= pin, GPIO_OUTPUT_ENABLE_ADDR);
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}
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}
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static inline void cfg_output_bit(const struct gpio_efinix_sapphire_cfg *config, gpio_pin_t pin,
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uint32_t value)
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{
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uint32_t c_reg_val = sys_read32(GPIO_OUTPUT_ADDR);
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if (value == GPIO_LOW) {
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sys_write32(c_reg_val &= ~pin, GPIO_OUTPUT_ADDR);
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} else if (value == GPIO_HIGH) {
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sys_write32(c_reg_val |= pin, GPIO_OUTPUT_ADDR);
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}
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}
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/* To use the controller bare minimum as IO, Peripheral has to configure, */
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/* the Output enable register, b0 : Input, b1 : Output */
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static int gpio_efinix_sapphire_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
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/* Check if the controller supports the requested GPIO configuration. */
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if (flags & ~SUPPORTED_FLAGS) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_MASK) {
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/* Pin cannot be configured as input and output */
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return -ENOTSUP;
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} else if ((flags & GPIO_DIR_MASK) == GPIO_DISCONNECTED) {
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/* Pin has to be configured as input or output */
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return -ENOTSUP;
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}
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/* Configure the output register based on the direction flag */
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if (flags & GPIO_OUTPUT) {
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/* Set the pin as output */
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cfg_output_enable_bit(config, BIT(pin), GPIO_OUTPUT);
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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/* Set the pin to high */
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cfg_output_bit(config, BIT(pin), GPIO_HIGH);
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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/* Set the pin to low */
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cfg_output_bit(config, BIT(pin), GPIO_LOW);
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}
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} else {
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/* Set the pin as input */
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cfg_output_enable_bit(config, BIT(pin), GPIO_INPUT);
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}
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return 0;
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}
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static inline uint32_t get_port(const struct gpio_efinix_sapphire_cfg *config)
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{
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uint32_t c_reg_val = sys_read32(GPIO_OUTPUT_ADDR);
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return (c_reg_val & BIT_MASK(config->n_gpios));
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}
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static inline void set_port(const struct gpio_efinix_sapphire_cfg *config, uint32_t value)
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{
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sys_write32(value, GPIO_OUTPUT_ADDR);
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}
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static int gpio_efinix_sapphire_port_get_raw(const struct device *dev, gpio_port_value_t *value)
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{
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const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
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*value = get_port(config);
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return 0;
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}
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static int gpio_efinix_sapphire_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
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uint32_t c_reg_val = get_port(config);
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/* Sets ports value at one go */
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c_reg_val &= ~mask;
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c_reg_val |= (value & mask);
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set_port(config, c_reg_val);
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return 0;
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}
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static int gpio_efinix_sapphire_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
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uint32_t c_reg_val = get_port(config);
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/* Sets ports value at one go */
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c_reg_val |= pins;
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set_port(config, c_reg_val);
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return 0;
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}
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static int gpio_efinix_sapphire_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
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uint32_t c_reg_val = get_port(config);
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/* Sets ports value at one go */
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c_reg_val &= ~pins;
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set_port(config, c_reg_val);
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return 0;
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}
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static int gpio_efinix_sapphire_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
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uint32_t c_reg_val = get_port(config);
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/* Sets ports value at one go */
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c_reg_val ^= pins;
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set_port(config, c_reg_val);
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return 0;
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}
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static int gpio_efinix_sapphire_init(const struct device *dev)
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{
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const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
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if (config->n_gpios > 4) {
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return -EINVAL;
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}
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return 0;
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}
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/* API map */
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static const struct gpio_driver_api gpio_efinix_sapphire_api = {
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.pin_configure = gpio_efinix_sapphire_config,
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.port_get_raw = gpio_efinix_sapphire_port_get_raw,
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.port_set_masked_raw = gpio_efinix_sapphire_port_set_masked_raw,
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.port_set_bits_raw = gpio_efinix_sapphire_port_set_bits_raw,
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.port_clear_bits_raw = gpio_efinix_sapphire_port_clear_bits_raw,
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.port_toggle_bits = gpio_efinix_sapphire_port_toggle_bits,
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};
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#define GPIO_EFINIX_SAPPHIRE_INIT(n) \
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static struct gpio_efinix_sapphire_cfg gpio_efinix_sapphire_cfg_##n = { \
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.base_addr = DT_INST_REG_ADDR(n), \
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.n_gpios = DT_INST_PROP(n, ngpios), \
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}; \
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static struct gpio_efinix_sapphire_data gpio_efinix_sapphire_data_##n; \
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DEVICE_DT_INST_DEFINE(n, \
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gpio_efinix_sapphire_init, \
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NULL, \
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&gpio_efinix_sapphire_data_##n, \
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&gpio_efinix_sapphire_cfg_##n, \
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POST_KERNEL, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_efinix_sapphire_api \
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); \
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DT_INST_FOREACH_STATUS_OKAY(GPIO_EFINIX_SAPPHIRE_INIT)
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