330 lines
7.7 KiB
C
330 lines
7.7 KiB
C
/*
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* Copyright (c) 2019 Song Qiang <songqiang1304521@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief DMA low level driver implementation for F0/F1/F3/L0/L4 series SoCs.
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*/
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#include "dma_stm32.h"
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#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(dma_stm32_v2);
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uint32_t dma_stm32_id_to_stream(uint32_t id)
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{
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static const uint32_t stream_nr[] = {
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LL_DMA_CHANNEL_1,
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LL_DMA_CHANNEL_2,
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LL_DMA_CHANNEL_3,
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#if defined(LL_DMA_CHANNEL_4)
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LL_DMA_CHANNEL_4,
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LL_DMA_CHANNEL_5,
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#if defined(LL_DMA_CHANNEL_6)
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LL_DMA_CHANNEL_6,
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#if defined(LL_DMA_CHANNEL_7)
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LL_DMA_CHANNEL_7,
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#if defined(LL_DMA_CHANNEL_8)
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LL_DMA_CHANNEL_8,
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#endif /* LL_DMA_CHANNEL_8 */
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#endif /* LL_DMA_CHANNEL_7 */
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#endif /* LL_DMA_CHANNEL_6 */
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#endif /* LL_DMA_CHANNEL_4 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(stream_nr));
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return stream_nr[id];
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}
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void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_clear_flag_func func[] = {
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LL_DMA_ClearFlag_HT1,
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LL_DMA_ClearFlag_HT2,
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LL_DMA_ClearFlag_HT3,
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#if defined(LL_DMA_IFCR_CHTIF4)
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LL_DMA_ClearFlag_HT4,
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LL_DMA_ClearFlag_HT5,
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#if defined(LL_DMA_IFCR_CHTIF6)
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LL_DMA_ClearFlag_HT6,
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#if defined(LL_DMA_IFCR_CHTIF7)
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LL_DMA_ClearFlag_HT7,
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#if defined(LL_DMA_IFCR_CHTIF8)
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LL_DMA_ClearFlag_HT8,
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#endif /* LL_DMA_IFCR_CHTIF8 */
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#endif /* LL_DMA_IFCR_CHTIF7 */
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#endif /* LL_DMA_IFCR_CHTIF6 */
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#endif /* LL_DMA_IFCR_CHTIF4 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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func[id](DMAx);
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}
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void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_clear_flag_func func[] = {
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LL_DMA_ClearFlag_TC1,
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LL_DMA_ClearFlag_TC2,
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LL_DMA_ClearFlag_TC3,
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#if defined(LL_DMA_IFCR_CTCIF4)
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LL_DMA_ClearFlag_TC4,
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LL_DMA_ClearFlag_TC5,
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#if defined(LL_DMA_IFCR_CTCIF6)
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LL_DMA_ClearFlag_TC6,
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#if defined(LL_DMA_IFCR_CTCIF7)
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LL_DMA_ClearFlag_TC7,
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#if defined(LL_DMA_IFCR_CTCIF8)
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LL_DMA_ClearFlag_TC8,
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#endif /* LL_DMA_IFCR_CTCIF8 */
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#endif /* LL_DMA_IFCR_CTCIF7 */
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#endif /* LL_DMA_IFCR_CTCIF6 */
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#endif /* LL_DMA_IFCR_CTCIF4 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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func[id](DMAx);
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}
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bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_check_flag_func func[] = {
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LL_DMA_IsActiveFlag_HT1,
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LL_DMA_IsActiveFlag_HT2,
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LL_DMA_IsActiveFlag_HT3,
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#if defined(LL_DMA_IFCR_CHTIF4)
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LL_DMA_IsActiveFlag_HT4,
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LL_DMA_IsActiveFlag_HT5,
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#if defined(LL_DMA_IFCR_CHTIF6)
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LL_DMA_IsActiveFlag_HT6,
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#if defined(LL_DMA_IFCR_CHTIF7)
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LL_DMA_IsActiveFlag_HT7,
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#if defined(LL_DMA_IFCR_CHTIF8)
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LL_DMA_IsActiveFlag_HT8,
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#endif /* LL_DMA_IFCR_CHTIF8 */
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#endif /* LL_DMA_IFCR_CHTIF7 */
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#endif /* LL_DMA_IFCR_CHTIF6 */
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#endif /* LL_DMA_IFCR_CHTIF4 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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return func[id](DMAx);
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}
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bool dma_stm32_is_tc_active(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_check_flag_func func[] = {
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LL_DMA_IsActiveFlag_TC1,
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LL_DMA_IsActiveFlag_TC2,
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LL_DMA_IsActiveFlag_TC3,
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#if defined(LL_DMA_IFCR_CTCIF4)
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LL_DMA_IsActiveFlag_TC4,
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LL_DMA_IsActiveFlag_TC5,
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#if defined(LL_DMA_IFCR_CTCIF6)
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LL_DMA_IsActiveFlag_TC6,
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#if defined(LL_DMA_IFCR_CTCIF7)
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LL_DMA_IsActiveFlag_TC7,
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#if defined(LL_DMA_IFCR_CTCIF8)
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LL_DMA_IsActiveFlag_TC8,
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#endif /* LL_DMA_IFCR_CTCIF8 */
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#endif /* LL_DMA_IFCR_CTCIF7 */
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#endif /* LL_DMA_IFCR_CTCIF6 */
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#endif /* LL_DMA_IFCR_CTCIF4 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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return func[id](DMAx);
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}
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void dma_stm32_clear_te(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_clear_flag_func func[] = {
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LL_DMA_ClearFlag_TE1,
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LL_DMA_ClearFlag_TE2,
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LL_DMA_ClearFlag_TE3,
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#if defined(LL_DMA_IFCR_CTEIF4)
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LL_DMA_ClearFlag_TE4,
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LL_DMA_ClearFlag_TE5,
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#if defined(LL_DMA_IFCR_CTEIF6)
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LL_DMA_ClearFlag_TE6,
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#if defined(LL_DMA_IFCR_CTEIF7)
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LL_DMA_ClearFlag_TE7,
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#if defined(LL_DMA_IFCR_CTEIF8)
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LL_DMA_ClearFlag_TE8,
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#endif /* LL_DMA_IFCR_CTEIF4 */
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#endif /* LL_DMA_IFCR_CTEIF6 */
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#endif /* LL_DMA_IFCR_CTEIF7 */
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#endif /* LL_DMA_IFCR_CTEIF8 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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func[id](DMAx);
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}
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void dma_stm32_clear_gi(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_clear_flag_func func[] = {
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LL_DMA_ClearFlag_GI1,
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LL_DMA_ClearFlag_GI2,
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LL_DMA_ClearFlag_GI3,
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#if defined(LL_DMA_IFCR_CGIF4)
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LL_DMA_ClearFlag_GI4,
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LL_DMA_ClearFlag_GI5,
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#if defined(LL_DMA_IFCR_CGIF6)
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LL_DMA_ClearFlag_GI6,
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#if defined(LL_DMA_IFCR_CGIF7)
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LL_DMA_ClearFlag_GI7,
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#if defined(LL_DMA_IFCR_CGIF8)
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LL_DMA_ClearFlag_GI8,
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#endif /* LL_DMA_IFCR_CGIF4 */
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#endif /* LL_DMA_IFCR_CGIF6 */
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#endif /* LL_DMA_IFCR_CGIF7 */
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#endif /* LL_DMA_IFCR_CGIF8 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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func[id](DMAx);
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}
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bool dma_stm32_is_te_active(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_check_flag_func func[] = {
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LL_DMA_IsActiveFlag_TE1,
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LL_DMA_IsActiveFlag_TE2,
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LL_DMA_IsActiveFlag_TE3,
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#if defined(LL_DMA_IFCR_CTEIF4)
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LL_DMA_IsActiveFlag_TE4,
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LL_DMA_IsActiveFlag_TE5,
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#if defined(LL_DMA_IFCR_CTEIF6)
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LL_DMA_IsActiveFlag_TE6,
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#if defined(LL_DMA_IFCR_CTEIF7)
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LL_DMA_IsActiveFlag_TE7,
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#if defined(LL_DMA_IFCR_CTEIF8)
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LL_DMA_IsActiveFlag_TE8,
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#endif /* LL_DMA_IFCR_CTEIF4 */
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#endif /* LL_DMA_IFCR_CTEIF6 */
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#endif /* LL_DMA_IFCR_CTEIF7 */
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#endif /* LL_DMA_IFCR_CTEIF8 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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return func[id](DMAx);
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}
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bool dma_stm32_is_gi_active(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_check_flag_func func[] = {
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LL_DMA_IsActiveFlag_GI1,
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LL_DMA_IsActiveFlag_GI2,
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LL_DMA_IsActiveFlag_GI3,
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#if defined(LL_DMA_IFCR_CGIF4)
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LL_DMA_IsActiveFlag_GI4,
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LL_DMA_IsActiveFlag_GI5,
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#if defined(LL_DMA_IFCR_CGIF6)
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LL_DMA_IsActiveFlag_GI6,
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#if defined(LL_DMA_IFCR_CGIF7)
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LL_DMA_IsActiveFlag_GI7,
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#if defined(LL_DMA_IFCR_CGIF8)
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LL_DMA_IsActiveFlag_GI8,
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#endif /* LL_DMA_IFCR_CGIF4 */
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#endif /* LL_DMA_IFCR_CGIF6 */
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#endif /* LL_DMA_IFCR_CGIF7 */
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#endif /* LL_DMA_IFCR_CGIF8 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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return func[id](DMAx);
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}
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void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, uint32_t id)
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{
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LOG_INF("tc: %d, ht: %d, te: %d, gi: %d",
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dma_stm32_is_tc_active(dma, id),
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dma_stm32_is_ht_active(dma, id),
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dma_stm32_is_te_active(dma, id),
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dma_stm32_is_gi_active(dma, id));
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}
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bool stm32_dma_is_tc_irq_active(DMA_TypeDef *dma, uint32_t id)
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{
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return LL_DMA_IsEnabledIT_TC(dma, dma_stm32_id_to_stream(id)) &&
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dma_stm32_is_tc_active(dma, id);
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}
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bool stm32_dma_is_ht_irq_active(DMA_TypeDef *dma, uint32_t id)
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{
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return LL_DMA_IsEnabledIT_HT(dma, dma_stm32_id_to_stream(id)) &&
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dma_stm32_is_ht_active(dma, id);
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}
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static inline bool stm32_dma_is_te_irq_active(DMA_TypeDef *dma, uint32_t id)
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{
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return LL_DMA_IsEnabledIT_TE(dma, dma_stm32_id_to_stream(id)) &&
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dma_stm32_is_te_active(dma, id);
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}
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bool stm32_dma_is_irq_active(DMA_TypeDef *dma, uint32_t id)
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{
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return stm32_dma_is_tc_irq_active(dma, id) ||
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stm32_dma_is_ht_irq_active(dma, id) ||
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stm32_dma_is_te_irq_active(dma, id);
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}
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void stm32_dma_clear_stream_irq(DMA_TypeDef *dma, uint32_t id)
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{
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dma_stm32_clear_te(dma, id);
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}
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bool stm32_dma_is_irq_happened(DMA_TypeDef *dma, uint32_t id)
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{
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if (dma_stm32_is_te_active(dma, id)) {
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return true;
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}
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return false;
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}
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bool stm32_dma_is_unexpected_irq_happened(DMA_TypeDef *dma, uint32_t id)
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{
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/* Preserve for future amending. */
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return false;
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}
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void stm32_dma_enable_stream(DMA_TypeDef *dma, uint32_t id)
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{
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LL_DMA_EnableChannel(dma, dma_stm32_id_to_stream(id));
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}
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bool stm32_dma_is_enabled_stream(DMA_TypeDef *dma, uint32_t id)
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{
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if (LL_DMA_IsEnabledChannel(dma, dma_stm32_id_to_stream(id)) == 1) {
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return true;
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}
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return false;
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}
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int stm32_dma_disable_stream(DMA_TypeDef *dma, uint32_t id)
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{
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LL_DMA_DisableChannel(dma, dma_stm32_id_to_stream(id));
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if (!LL_DMA_IsEnabledChannel(dma, dma_stm32_id_to_stream(id))) {
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return 0;
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}
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return -EAGAIN;
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}
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