225 lines
7.8 KiB
C
225 lines
7.8 KiB
C
/*
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* Copyright 2023-2024 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/dma.h>
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#include <zephyr/drivers/dma/dma_mcux_pxp.h>
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#include <zephyr/devicetree.h>
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#include <fsl_pxp.h>
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#ifdef CONFIG_HAS_MCUX_CACHE
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#include <fsl_cache.h>
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#endif
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#define DT_DRV_COMPAT nxp_pxp
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(dma_mcux_pxp, CONFIG_DMA_LOG_LEVEL);
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struct dma_mcux_pxp_config {
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PXP_Type *base;
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void (*irq_config_func)(const struct device *dev);
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};
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struct dma_mcux_pxp_data {
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void *user_data;
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dma_callback_t dma_callback;
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uint32_t ps_buf_addr;
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uint32_t ps_buf_size;
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uint32_t out_buf_addr;
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uint32_t out_buf_size;
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};
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static void dma_mcux_pxp_irq_handler(const struct device *dev)
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{
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const struct dma_mcux_pxp_config *config = dev->config;
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struct dma_mcux_pxp_data *data = dev->data;
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PXP_ClearStatusFlags(config->base, kPXP_CompleteFlag);
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#ifdef CONFIG_HAS_MCUX_CACHE
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DCACHE_InvalidateByRange((uint32_t)data->out_buf_addr, data->out_buf_size);
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#endif
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if (data->dma_callback) {
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data->dma_callback(dev, data->user_data, 0, 0);
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}
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}
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/* Configure a channel */
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static int dma_mcux_pxp_configure(const struct device *dev, uint32_t channel,
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struct dma_config *config)
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{
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const struct dma_mcux_pxp_config *dev_config = dev->config;
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struct dma_mcux_pxp_data *dev_data = dev->data;
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pxp_ps_buffer_config_t ps_buffer_cfg;
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pxp_output_buffer_config_t output_buffer_cfg;
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uint8_t bytes_per_pixel;
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pxp_rotate_degree_t rotate;
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pxp_flip_mode_t flip;
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ARG_UNUSED(channel);
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if (config->channel_direction != MEMORY_TO_MEMORY) {
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return -ENOTSUP;
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}
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/*
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* Use the DMA slot value to get the pixel format and rotation
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* settings
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*/
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switch ((config->dma_slot & DMA_MCUX_PXP_CMD_MASK) >> DMA_MCUX_PXP_CMD_SHIFT) {
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case DMA_MCUX_PXP_CMD_ROTATE_0:
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rotate = kPXP_Rotate0;
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break;
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case DMA_MCUX_PXP_CMD_ROTATE_90:
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rotate = kPXP_Rotate90;
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break;
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case DMA_MCUX_PXP_CMD_ROTATE_180:
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rotate = kPXP_Rotate180;
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break;
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case DMA_MCUX_PXP_CMD_ROTATE_270:
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rotate = kPXP_Rotate270;
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break;
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default:
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return -ENOTSUP;
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}
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switch ((config->dma_slot & DMA_MCUX_PXP_FMT_MASK) >> DMA_MCUX_PXP_FMT_SHIFT) {
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case DMA_MCUX_PXP_FMT_RGB565:
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ps_buffer_cfg.pixelFormat = kPXP_PsPixelFormatRGB565;
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output_buffer_cfg.pixelFormat = kPXP_OutputPixelFormatRGB565;
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bytes_per_pixel = 2;
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break;
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case DMA_MCUX_PXP_FMT_RGB888:
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#if (!(defined(FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT) && \
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FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT)) && \
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(!(defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3))
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ps_buffer_cfg.pixelFormat = kPXP_PsPixelFormatARGB8888;
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#else
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ps_buffer_cfg.pixelFormat = kPXP_PsPixelFormatRGB888;
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#endif
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output_buffer_cfg.pixelFormat = kPXP_OutputPixelFormatRGB888;
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bytes_per_pixel = 3;
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break;
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case DMA_MCUX_PXP_FMT_ARGB8888:
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ps_buffer_cfg.pixelFormat = kPXP_PsPixelFormatARGB8888;
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output_buffer_cfg.pixelFormat = kPXP_OutputPixelFormatARGB8888;
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bytes_per_pixel = 4;
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break;
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default:
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return -ENOTSUP;
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}
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/*
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* Use the DMA linked_channel value to get the flip settings.
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*/
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switch ((config->linked_channel & DMA_MCUX_PXP_FLIP_MASK) >> DMA_MCUX_PXP_FLIP_SHIFT) {
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case DMA_MCUX_PXP_FLIP_DISABLE:
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flip = kPXP_FlipDisable;
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break;
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case DMA_MCUX_PXP_FLIP_HORIZONTAL:
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flip = kPXP_FlipHorizontal;
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break;
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case DMA_MCUX_PXP_FLIP_VERTICAL:
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flip = kPXP_FlipVertical;
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break;
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case DMA_MCUX_PXP_FLIP_BOTH:
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flip = kPXP_FlipBoth;
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break;
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default:
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return -ENOTSUP;
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}
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DCACHE_CleanByRange((uint32_t)config->head_block->source_address,
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config->head_block->block_size);
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/*
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* Some notes on how specific fields of the DMA config are used by
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* the PXP:
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* head block source address: PS buffer source address
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* head block destination address: Output buffer address
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* head block block size: size of destination and source buffer
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* source data size: width of source buffer in bytes (pitch)
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* source burst length: height of source buffer in pixels
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* dest data size: width of destination buffer in bytes (pitch)
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* dest burst length: height of destination buffer in pixels
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*/
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ps_buffer_cfg.swapByte = false;
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ps_buffer_cfg.bufferAddr = config->head_block->source_address;
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ps_buffer_cfg.bufferAddrU = 0U;
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ps_buffer_cfg.bufferAddrV = 0U;
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ps_buffer_cfg.pitchBytes = config->source_data_size;
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PXP_SetProcessSurfaceBufferConfig(dev_config->base, &ps_buffer_cfg);
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output_buffer_cfg.interlacedMode = kPXP_OutputProgressive;
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output_buffer_cfg.buffer0Addr = config->head_block->dest_address;
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output_buffer_cfg.buffer1Addr = 0U;
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output_buffer_cfg.pitchBytes = config->dest_data_size;
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output_buffer_cfg.width = (config->dest_data_size / bytes_per_pixel);
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output_buffer_cfg.height = config->dest_burst_length;
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PXP_SetOutputBufferConfig(dev_config->base, &output_buffer_cfg);
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/* We only support a process surface that covers the full buffer */
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PXP_SetProcessSurfacePosition(dev_config->base, 0U, 0U, output_buffer_cfg.width,
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output_buffer_cfg.height);
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/* Setup rotation */
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PXP_SetRotateConfig(dev_config->base, kPXP_RotateProcessSurface, rotate, flip);
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dev_data->ps_buf_addr = config->head_block->source_address;
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dev_data->ps_buf_size = config->head_block->block_size;
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dev_data->out_buf_addr = config->head_block->dest_address;
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dev_data->out_buf_size = config->head_block->block_size;
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dev_data->dma_callback = config->dma_callback;
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dev_data->user_data = config->user_data;
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return 0;
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}
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static int dma_mcux_pxp_start(const struct device *dev, uint32_t channel)
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{
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const struct dma_mcux_pxp_config *config = dev->config;
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struct dma_mcux_pxp_data *data = dev->data;
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#ifdef CONFIG_HAS_MCUX_CACHE
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DCACHE_CleanByRange((uint32_t)data->ps_buf_addr, data->ps_buf_size);
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#endif
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ARG_UNUSED(channel);
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PXP_Start(config->base);
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return 0;
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}
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static const struct dma_driver_api dma_mcux_pxp_api = {
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.config = dma_mcux_pxp_configure,
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.start = dma_mcux_pxp_start,
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};
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static int dma_mcux_pxp_init(const struct device *dev)
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{
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const struct dma_mcux_pxp_config *config = dev->config;
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PXP_Init(config->base);
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PXP_SetProcessSurfaceBackGroundColor(config->base, 0U);
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/* Disable alpha surface and CSC1 */
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PXP_SetAlphaSurfacePosition(config->base, 0xFFFFU, 0xFFFFU, 0U, 0U);
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PXP_EnableCsc1(config->base, false);
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PXP_EnableInterrupts(config->base, kPXP_CompleteInterruptEnable);
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config->irq_config_func(dev);
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return 0;
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}
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#define DMA_INIT(n) \
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static void dma_pxp_config_func##n(const struct device *dev) \
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{ \
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IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \
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(IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
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dma_mcux_pxp_irq_handler, DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ(n, irq));)) \
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} \
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\
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static const struct dma_mcux_pxp_config dma_config_##n = { \
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.base = (PXP_Type *)DT_INST_REG_ADDR(n), \
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.irq_config_func = dma_pxp_config_func##n, \
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}; \
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\
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static struct dma_mcux_pxp_data dma_data_##n; \
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\
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DEVICE_DT_INST_DEFINE(n, &dma_mcux_pxp_init, NULL, &dma_data_##n, &dma_config_##n, \
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PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, &dma_mcux_pxp_api);
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DT_INST_FOREACH_STATUS_OKAY(DMA_INIT)
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