575 lines
17 KiB
C
575 lines
17 KiB
C
/* swap_macros.h - helper macros for context switch */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_ARCH_ARC_INCLUDE_SWAP_MACROS_H_
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#define ZEPHYR_ARCH_ARC_INCLUDE_SWAP_MACROS_H_
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#include <zephyr/kernel_structs.h>
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#include <offsets_short.h>
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#include <zephyr/toolchain.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/arch/arc/tool-compat.h>
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#include <zephyr/arch/arc/asm-compat/assembler.h>
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#include <zephyr/kernel.h>
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#include "../core/dsp/swap_dsp_macros.h"
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#ifdef _ASMLANGUAGE
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/* save callee regs of current thread in r2 */
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.macro _save_callee_saved_regs
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SUBR sp, sp, ___callee_saved_stack_t_SIZEOF
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/* save regs on stack */
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STR r13, sp, ___callee_saved_stack_t_r13_OFFSET
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STR r14, sp, ___callee_saved_stack_t_r14_OFFSET
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STR r15, sp, ___callee_saved_stack_t_r15_OFFSET
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STR r16, sp, ___callee_saved_stack_t_r16_OFFSET
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STR r17, sp, ___callee_saved_stack_t_r17_OFFSET
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STR r18, sp, ___callee_saved_stack_t_r18_OFFSET
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STR r19, sp, ___callee_saved_stack_t_r19_OFFSET
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STR r20, sp, ___callee_saved_stack_t_r20_OFFSET
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STR r21, sp, ___callee_saved_stack_t_r21_OFFSET
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STR r22, sp, ___callee_saved_stack_t_r22_OFFSET
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STR r23, sp, ___callee_saved_stack_t_r23_OFFSET
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STR r24, sp, ___callee_saved_stack_t_r24_OFFSET
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STR r25, sp, ___callee_saved_stack_t_r25_OFFSET
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STR r26, sp, ___callee_saved_stack_t_r26_OFFSET
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STR fp, sp, ___callee_saved_stack_t_fp_OFFSET
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#ifdef CONFIG_USERSPACE
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#ifdef CONFIG_ARC_HAS_SECURE
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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lr r13, [_ARC_V2_SEC_U_SP]
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st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
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lr r13, [_ARC_V2_SEC_K_SP]
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st_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
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#else
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lr r13, [_ARC_V2_USER_SP]
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st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
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lr r13, [_ARC_V2_KERNEL_SP]
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st_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
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#endif /* CONFIG_ARC_SECURE_FIRMWARE */
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#else
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lr r13, [_ARC_V2_USER_SP]
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st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
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#endif
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#endif
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STR r30, sp, ___callee_saved_stack_t_r30_OFFSET
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#ifdef CONFIG_ARC_HAS_ACCL_REGS
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STR r58, sp, ___callee_saved_stack_t_r58_OFFSET
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#ifndef CONFIG_64BIT
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STR r59, sp, ___callee_saved_stack_t_r59_OFFSET
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#endif /* !CONFIG_64BIT */
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#endif
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#ifdef CONFIG_FPU_SHARING
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ld_s r13, [r2, ___thread_base_t_user_options_OFFSET]
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bbit0 r13, K_FP_IDX, fpu_skip_save
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lr r13, [_ARC_V2_FPU_STATUS]
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st_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
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lr r13, [_ARC_V2_FPU_CTRL]
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st_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
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#ifdef CONFIG_FP_FPU_DA
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lr r13, [_ARC_V2_FPU_DPFP1L]
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st_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
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lr r13, [_ARC_V2_FPU_DPFP1H]
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st_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
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lr r13, [_ARC_V2_FPU_DPFP2L]
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st_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
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lr r13, [_ARC_V2_FPU_DPFP2H]
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st_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
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#endif
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#endif
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fpu_skip_save :
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_save_dsp_regs
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/* save stack pointer in struct k_thread */
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STR sp, r2, _thread_offset_to_sp
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.endm
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/* load the callee regs of thread (in r2)*/
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.macro _load_callee_saved_regs
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/* restore stack pointer from struct k_thread */
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LDR sp, r2, _thread_offset_to_sp
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#ifdef CONFIG_ARC_HAS_ACCL_REGS
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LDR r58, sp, ___callee_saved_stack_t_r58_OFFSET
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#ifndef CONFIG_64BIT
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LDR r59, sp, ___callee_saved_stack_t_r59_OFFSET
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#endif /* !CONFIG_64BIT */
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#endif
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#ifdef CONFIG_FPU_SHARING
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ld_s r13, [r2, ___thread_base_t_user_options_OFFSET]
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bbit0 r13, K_FP_IDX, fpu_skip_load
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ld_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
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sr r13, [_ARC_V2_FPU_STATUS]
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ld_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
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sr r13, [_ARC_V2_FPU_CTRL]
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#ifdef CONFIG_FP_FPU_DA
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ld_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
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sr r13, [_ARC_V2_FPU_DPFP1L]
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ld_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
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sr r13, [_ARC_V2_FPU_DPFP1H]
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ld_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
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sr r13, [_ARC_V2_FPU_DPFP2L]
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ld_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
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sr r13, [_ARC_V2_FPU_DPFP2H]
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#endif
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#endif
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fpu_skip_load :
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_load_dsp_regs
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#ifdef CONFIG_USERSPACE
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#ifdef CONFIG_ARC_HAS_SECURE
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
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sr r13, [_ARC_V2_SEC_U_SP]
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ld_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
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sr r13, [_ARC_V2_SEC_K_SP]
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#else
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ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
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sr r13, [_ARC_V2_USER_SP]
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ld_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
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sr r13, [_ARC_V2_KERNEL_SP]
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#endif /* CONFIG_ARC_SECURE_FIRMWARE */
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#else
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ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
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sr r13, [_ARC_V2_USER_SP]
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#endif
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#endif
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LDR r13, sp, ___callee_saved_stack_t_r13_OFFSET
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LDR r14, sp, ___callee_saved_stack_t_r14_OFFSET
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LDR r15, sp, ___callee_saved_stack_t_r15_OFFSET
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LDR r16, sp, ___callee_saved_stack_t_r16_OFFSET
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LDR r17, sp, ___callee_saved_stack_t_r17_OFFSET
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LDR r18, sp, ___callee_saved_stack_t_r18_OFFSET
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LDR r19, sp, ___callee_saved_stack_t_r19_OFFSET
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LDR r20, sp, ___callee_saved_stack_t_r20_OFFSET
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LDR r21, sp, ___callee_saved_stack_t_r21_OFFSET
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LDR r22, sp, ___callee_saved_stack_t_r22_OFFSET
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LDR r23, sp, ___callee_saved_stack_t_r23_OFFSET
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LDR r24, sp, ___callee_saved_stack_t_r24_OFFSET
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LDR r25, sp, ___callee_saved_stack_t_r25_OFFSET
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LDR r26, sp, ___callee_saved_stack_t_r26_OFFSET
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LDR fp, sp, ___callee_saved_stack_t_fp_OFFSET
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LDR r30, sp, ___callee_saved_stack_t_r30_OFFSET
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ADDR sp, sp, ___callee_saved_stack_t_SIZEOF
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.endm
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/* discard callee regs */
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.macro _discard_callee_saved_regs
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ADDR sp, sp, ___callee_saved_stack_t_SIZEOF
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.endm
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/*
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* Must be called with interrupts locked or in P0.
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* Upon exit, sp will be pointing to the stack frame.
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*/
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.macro _create_irq_stack_frame
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SUBR sp, sp, ___isf_t_SIZEOF
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STR blink, sp, ___isf_t_blink_OFFSET
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/* store these right away so we can use them if needed */
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STR r13, sp, ___isf_t_r13_OFFSET
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STR r12, sp, ___isf_t_r12_OFFSET
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STR r11, sp, ___isf_t_r11_OFFSET
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STR r10, sp, ___isf_t_r10_OFFSET
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STR r9, sp, ___isf_t_r9_OFFSET
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STR r8, sp, ___isf_t_r8_OFFSET
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STR r7, sp, ___isf_t_r7_OFFSET
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STR r6, sp, ___isf_t_r6_OFFSET
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STR r5, sp, ___isf_t_r5_OFFSET
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STR r4, sp, ___isf_t_r4_OFFSET
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STR r3, sp, ___isf_t_r3_OFFSET
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STR r2, sp, ___isf_t_r2_OFFSET
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STR r1, sp, ___isf_t_r1_OFFSET
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STR r0, sp, ___isf_t_r0_OFFSET
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#ifdef CONFIG_ARC_HAS_ZOL
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MOVR r0, lp_count
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STR r0, sp, ___isf_t_lp_count_OFFSET
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LRR r1, [_ARC_V2_LP_START]
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LRR r0, [_ARC_V2_LP_END]
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STR r1, sp, ___isf_t_lp_start_OFFSET
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STR r0, sp, ___isf_t_lp_end_OFFSET
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#endif /* CONFIG_ARC_HAS_ZOL */
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#ifdef CONFIG_CODE_DENSITY
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lr r1, [_ARC_V2_JLI_BASE]
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lr r0, [_ARC_V2_LDI_BASE]
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lr r2, [_ARC_V2_EI_BASE]
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st_s r1, [sp, ___isf_t_jli_base_OFFSET]
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st_s r0, [sp, ___isf_t_ldi_base_OFFSET]
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st_s r2, [sp, ___isf_t_ei_base_OFFSET]
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#endif
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.endm
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/*
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* Must be called with interrupts locked or in P0.
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* sp must be pointing the to stack frame.
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*/
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.macro _pop_irq_stack_frame
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LDR blink, sp, ___isf_t_blink_OFFSET
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#ifdef CONFIG_CODE_DENSITY
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ld_s r1, [sp, ___isf_t_jli_base_OFFSET]
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ld_s r0, [sp, ___isf_t_ldi_base_OFFSET]
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ld_s r2, [sp, ___isf_t_ei_base_OFFSET]
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sr r1, [_ARC_V2_JLI_BASE]
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sr r0, [_ARC_V2_LDI_BASE]
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sr r2, [_ARC_V2_EI_BASE]
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#endif
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#ifdef CONFIG_ARC_HAS_ZOL
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LDR r0, sp, ___isf_t_lp_count_OFFSET
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MOVR lp_count, r0
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LDR r1, sp, ___isf_t_lp_start_OFFSET
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LDR r0, sp, ___isf_t_lp_end_OFFSET
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SRR r1, [_ARC_V2_LP_START]
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SRR r0, [_ARC_V2_LP_END]
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#endif /* CONFIG_ARC_HAS_ZOL */
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LDR r13, sp, ___isf_t_r13_OFFSET
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LDR r12, sp, ___isf_t_r12_OFFSET
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LDR r11, sp, ___isf_t_r11_OFFSET
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LDR r10, sp, ___isf_t_r10_OFFSET
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LDR r9, sp, ___isf_t_r9_OFFSET
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LDR r8, sp, ___isf_t_r8_OFFSET
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LDR r7, sp, ___isf_t_r7_OFFSET
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LDR r6, sp, ___isf_t_r6_OFFSET
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LDR r5, sp, ___isf_t_r5_OFFSET
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LDR r4, sp, ___isf_t_r4_OFFSET
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LDR r3, sp, ___isf_t_r3_OFFSET
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LDR r2, sp, ___isf_t_r2_OFFSET
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LDR r1, sp, ___isf_t_r1_OFFSET
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LDR r0, sp, ___isf_t_r0_OFFSET
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/*
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* All gprs have been reloaded, the only one that is still usable is
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* ilink.
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*
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* The pc and status32 values will still be on the stack. We cannot
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* pop them yet because the callers of _pop_irq_stack_frame must reload
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* status32 differently depending on the execution context they are
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* running in (arch_switch(), firq or exception).
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*/
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ADDR sp, sp, ___isf_t_SIZEOF
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.endm
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/*
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* To use this macro, r2 should have the value of thread struct pointer to
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* _kernel.current. r3 is a scratch reg.
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*/
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.macro _load_stack_check_regs
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#if defined(CONFIG_ARC_SECURE_FIRMWARE)
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ld r3, [r2, _thread_offset_to_k_stack_base]
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sr r3, [_ARC_V2_S_KSTACK_BASE]
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ld r3, [r2, _thread_offset_to_k_stack_top]
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sr r3, [_ARC_V2_S_KSTACK_TOP]
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#ifdef CONFIG_USERSPACE
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ld r3, [r2, _thread_offset_to_u_stack_base]
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sr r3, [_ARC_V2_S_USTACK_BASE]
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ld r3, [r2, _thread_offset_to_u_stack_top]
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sr r3, [_ARC_V2_S_USTACK_TOP]
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#endif
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#else /* CONFIG_ARC_HAS_SECURE */
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ld r3, [r2, _thread_offset_to_k_stack_base]
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sr r3, [_ARC_V2_KSTACK_BASE]
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ld r3, [r2, _thread_offset_to_k_stack_top]
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sr r3, [_ARC_V2_KSTACK_TOP]
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#ifdef CONFIG_USERSPACE
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ld r3, [r2, _thread_offset_to_u_stack_base]
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sr r3, [_ARC_V2_USTACK_BASE]
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ld r3, [r2, _thread_offset_to_u_stack_top]
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sr r3, [_ARC_V2_USTACK_TOP]
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#endif
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#endif /* CONFIG_ARC_SECURE_FIRMWARE */
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.endm
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/* check and increase the interrupt nest counter
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* after increase, check whether nest counter == 1
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* the result will be EQ bit of status32
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* two temp regs are needed
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*/
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.macro _check_and_inc_int_nest_counter, reg1, reg2
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#ifdef CONFIG_SMP
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/* get pointer to _cpu_t of this CPU */
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_get_cpu_id MACRO_ARG(reg1)
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ASLR MACRO_ARG(reg1), MACRO_ARG(reg1), ARC_REGSHIFT
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LDR MACRO_ARG(reg1), MACRO_ARG(reg1), _curr_cpu
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/* _cpu_t.nested is 32 bit despite of platform bittnes */
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ld MACRO_ARG(reg2), [MACRO_ARG(reg1), ___cpu_t_nested_OFFSET]
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#else
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MOVR MACRO_ARG(reg1), _kernel
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/* z_kernel.nested is 32 bit despite of platform bittnes */
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ld MACRO_ARG(reg2), [MACRO_ARG(reg1), _kernel_offset_to_nested]
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#endif
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add MACRO_ARG(reg2), MACRO_ARG(reg2), 1
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#ifdef CONFIG_SMP
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st MACRO_ARG(reg2), [MACRO_ARG(reg1), ___cpu_t_nested_OFFSET]
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#else
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st MACRO_ARG(reg2), [MACRO_ARG(reg1), _kernel_offset_to_nested]
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#endif
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cmp MACRO_ARG(reg2), 1
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.endm
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/* decrease interrupt stack nest counter
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* the counter > 0, interrupt stack is used, or
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* not used
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*/
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.macro _dec_int_nest_counter, reg1, reg2
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#ifdef CONFIG_SMP
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/* get pointer to _cpu_t of this CPU */
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_get_cpu_id MACRO_ARG(reg1)
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ASLR MACRO_ARG(reg1), MACRO_ARG(reg1), ARC_REGSHIFT
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LDR MACRO_ARG(reg1), MACRO_ARG(reg1), _curr_cpu
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/* _cpu_t.nested is 32 bit despite of platform bittnes */
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ld MACRO_ARG(reg2), [MACRO_ARG(reg1), ___cpu_t_nested_OFFSET]
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#else
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MOVR MACRO_ARG(reg1), _kernel
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/* z_kernel.nested is 32 bit despite of platform bittnes */
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ld MACRO_ARG(reg2), [MACRO_ARG(reg1), _kernel_offset_to_nested]
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#endif
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sub MACRO_ARG(reg2), MACRO_ARG(reg2), 1
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#ifdef CONFIG_SMP
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st MACRO_ARG(reg2), [MACRO_ARG(reg1), ___cpu_t_nested_OFFSET]
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#else
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st MACRO_ARG(reg2), [MACRO_ARG(reg1), _kernel_offset_to_nested]
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#endif
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.endm
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/* If multi bits in IRQ_ACT are set, i.e. last bit != fist bit, it's
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* in nest interrupt. The result will be EQ bit of status32
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* need two temp reg to do this
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*/
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.macro _check_nest_int_by_irq_act, reg1, reg2
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lr MACRO_ARG(reg1), [_ARC_V2_AUX_IRQ_ACT]
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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and MACRO_ARG(reg1), MACRO_ARG(reg1), ((1 << ARC_N_IRQ_START_LEVEL) - 1)
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#else
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and MACRO_ARG(reg1), MACRO_ARG(reg1), 0xffff
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#endif
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ffs MACRO_ARG(reg2), MACRO_ARG(reg1)
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fls MACRO_ARG(reg1), MACRO_ARG(reg1)
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cmp MACRO_ARG(reg1), MACRO_ARG(reg2)
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.endm
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/* macro to get id of current cpu
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* the result will be in reg (a reg)
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*/
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.macro _get_cpu_id, reg
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LRR MACRO_ARG(reg), [_ARC_V2_IDENTITY]
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xbfu MACRO_ARG(reg), MACRO_ARG(reg), 0xe8
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.endm
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/* macro to get the interrupt stack of current cpu
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* the result will be in irq_sp (a reg)
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*/
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.macro _get_curr_cpu_irq_stack, irq_sp
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#ifdef CONFIG_SMP
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/* get pointer to _cpu_t of this CPU */
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_get_cpu_id MACRO_ARG(irq_sp)
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ASLR MACRO_ARG(irq_sp), MACRO_ARG(irq_sp), ARC_REGSHIFT
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LDR MACRO_ARG(irq_sp), MACRO_ARG(irq_sp), _curr_cpu
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/* get pointer to irq_stack itself */
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LDR MACRO_ARG(irq_sp), MACRO_ARG(irq_sp), ___cpu_t_irq_stack_OFFSET
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#else
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MOVR MACRO_ARG(irq_sp), _kernel
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LDR MACRO_ARG(irq_sp), MACRO_ARG(irq_sp), _kernel_offset_to_irq_stack
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#endif
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.endm
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/* macro to push aux reg through reg */
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.macro PUSHAX, reg, aux
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|
LRR MACRO_ARG(reg), [MACRO_ARG(aux)]
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PUSHR MACRO_ARG(reg)
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|
.endm
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|
|
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/* macro to pop aux reg through reg */
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|
.macro POPAX, reg, aux
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|
POPR MACRO_ARG(reg)
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SRR MACRO_ARG(reg), [MACRO_ARG(aux)]
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|
.endm
|
|
|
|
|
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/* macro to store old thread call regs */
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|
.macro _store_old_thread_callee_regs
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|
|
|
_save_callee_saved_regs
|
|
/* Save old thread into switch handle which is required by z_sched_switch_spin.
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|
* NOTE: we shouldn't save anything related to old thread context after this point!
|
|
* TODO: we should add SMP write-after-write data memory barrier here, as we want all
|
|
* previous writes completed before setting switch_handle which is polled by other cores
|
|
* in z_sched_switch_spin in case of SMP. Though it's not likely that this issue
|
|
* will reproduce in real world as there is some gap before reading switch_handle and
|
|
* reading rest of the data we've stored before.
|
|
*/
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|
STR r2, r2, ___thread_t_switch_handle_OFFSET
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|
.endm
|
|
|
|
/* macro to store old thread call regs in interrupt*/
|
|
.macro _irq_store_old_thread_callee_regs
|
|
#if defined(CONFIG_USERSPACE)
|
|
/*
|
|
* when USERSPACE is enabled, according to ARCv2 ISA, SP will be switched
|
|
* if interrupt comes out in user mode, and will be recorded in bit 31
|
|
* (U bit) of IRQ_ACT. when interrupt exits, SP will be switched back
|
|
* according to U bit.
|
|
*
|
|
* need to remember the user/kernel status of interrupted thread, will be
|
|
* restored when thread switched back
|
|
*
|
|
*/
|
|
lr r1, [_ARC_V2_AUX_IRQ_ACT]
|
|
and r3, r1, 0x80000000
|
|
push_s r3
|
|
|
|
bclr r1, r1, 31
|
|
sr r1, [_ARC_V2_AUX_IRQ_ACT]
|
|
#endif
|
|
_store_old_thread_callee_regs
|
|
.endm
|
|
|
|
/* macro to load new thread callee regs */
|
|
.macro _load_new_thread_callee_regs
|
|
#ifdef CONFIG_ARC_STACK_CHECKING
|
|
_load_stack_check_regs
|
|
#endif
|
|
/*
|
|
* _load_callee_saved_regs expects incoming thread in r2.
|
|
* _load_callee_saved_regs restores the stack pointer.
|
|
*/
|
|
_load_callee_saved_regs
|
|
|
|
#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
|
|
push_s r2
|
|
bl configure_mpu_thread
|
|
pop_s r2
|
|
#endif
|
|
/* _thread_arch.relinquish_cause is 32 bit despite of platform bittnes */
|
|
ld r3, [r2, _thread_offset_to_relinquish_cause]
|
|
.endm
|
|
|
|
|
|
/* when switch to thread caused by coop, some status regs need to set */
|
|
.macro _set_misc_regs_irq_switch_from_coop
|
|
#ifdef CONFIG_ARC_SECURE_FIRMWARE
|
|
/* must return to secure mode, so set IRM bit to 1 */
|
|
lr r0, [_ARC_V2_SEC_STAT]
|
|
bset r0, r0, _ARC_V2_SEC_STAT_IRM_BIT
|
|
sflag r0
|
|
#endif
|
|
.endm
|
|
|
|
/* when switch to thread caused by irq, some status regs need to set */
|
|
.macro _set_misc_regs_irq_switch_from_irq
|
|
#if defined(CONFIG_USERSPACE)
|
|
/*
|
|
* need to recover the user/kernel status of interrupted thread
|
|
*/
|
|
pop_s r3
|
|
lr r2, [_ARC_V2_AUX_IRQ_ACT]
|
|
or r2, r2, r3
|
|
sr r2, [_ARC_V2_AUX_IRQ_ACT]
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARC_SECURE_FIRMWARE
|
|
/* here need to recover SEC_STAT.IRM bit */
|
|
pop_s r3
|
|
sflag r3
|
|
#endif
|
|
.endm
|
|
|
|
/* macro to get next switch handle in assembly */
|
|
.macro _get_next_switch_handle
|
|
PUSHR r2
|
|
MOVR r0, sp
|
|
bl z_arch_get_next_switch_handle
|
|
POPR r2
|
|
.endm
|
|
|
|
/* macro to disable stack checking in assembly, need a GPR
|
|
* to do this
|
|
*/
|
|
.macro _disable_stack_checking, reg
|
|
#ifdef CONFIG_ARC_STACK_CHECKING
|
|
#ifdef CONFIG_ARC_SECURE_FIRMWARE
|
|
lr MACRO_ARG(reg), [_ARC_V2_SEC_STAT]
|
|
bclr MACRO_ARG(reg), MACRO_ARG(reg), _ARC_V2_SEC_STAT_SSC_BIT
|
|
sflag MACRO_ARG(reg)
|
|
|
|
#else
|
|
lr MACRO_ARG(reg), [_ARC_V2_STATUS32]
|
|
bclr MACRO_ARG(reg), MACRO_ARG(reg), _ARC_V2_STATUS32_SC_BIT
|
|
kflag MACRO_ARG(reg)
|
|
#endif
|
|
#endif
|
|
.endm
|
|
|
|
/* macro to enable stack checking in assembly, need a GPR
|
|
* to do this
|
|
*/
|
|
.macro _enable_stack_checking, reg
|
|
#ifdef CONFIG_ARC_STACK_CHECKING
|
|
#ifdef CONFIG_ARC_SECURE_FIRMWARE
|
|
lr MACRO_ARG(reg), [_ARC_V2_SEC_STAT]
|
|
bset MACRO_ARG(reg), MACRO_ARG(reg), _ARC_V2_SEC_STAT_SSC_BIT
|
|
sflag MACRO_ARG(reg)
|
|
#else
|
|
lr MACRO_ARG(reg), [_ARC_V2_STATUS32]
|
|
bset MACRO_ARG(reg), MACRO_ARG(reg), _ARC_V2_STATUS32_SC_BIT
|
|
kflag MACRO_ARG(reg)
|
|
#endif
|
|
#endif
|
|
.endm
|
|
|
|
|
|
#define __arc_u9_max (255)
|
|
#define __arc_u9_min (-256)
|
|
#define __arc_ldst32_as_shift 2
|
|
|
|
/*
|
|
* When we accessing bloated struct member we can exceed u9 operand in store
|
|
* instruction. So we can use _st32_huge_offset macro instead
|
|
*/
|
|
.macro _st32_huge_offset, d, s, offset, temp
|
|
.if MACRO_ARG(offset) <= __arc_u9_max && MACRO_ARG(offset) >= __arc_u9_min
|
|
st MACRO_ARG(d), [MACRO_ARG(s), MACRO_ARG(offset)]
|
|
/* Technically we can optimize with .as both big positive and negative offsets here, but
|
|
* as we use only positive offsets in hand-written assembly code we keep only
|
|
* positive offset case here for simplicity.
|
|
*/
|
|
.elseif !(MACRO_ARG(offset) % (1 << __arc_ldst32_as_shift)) && \
|
|
MACRO_ARG(offset) <= (__arc_u9_max << __arc_ldst32_as_shift) && \
|
|
MACRO_ARG(offset) >= 0
|
|
st.as MACRO_ARG(d), [MACRO_ARG(s), MACRO_ARG(offset) >> __arc_ldst32_as_shift]
|
|
.else
|
|
ADDR MACRO_ARG(temp), MACRO_ARG(s), MACRO_ARG(offset)
|
|
st MACRO_ARG(d), [MACRO_ARG(temp)]
|
|
.endif
|
|
.endm
|
|
|
|
#endif /* _ASMLANGUAGE */
|
|
|
|
#endif /* ZEPHYR_ARCH_ARC_INCLUDE_SWAP_MACROS_H_ */
|