8014e075f4
Previously, context switching on x86 with memory protection enabled involved walking the page tables, de-configuring all the partitions in the outgoing thread's memory domain, and then configuring all the partitions in the incoming thread's domain, on a global set of page tables. We now have a much faster design. Each thread has reserved in its stack object a number of pages to store page directories and page tables pertaining to the system RAM area. Each thread also has a toplevel PDPT which is configured to use the per-thread tables for system RAM, and the global tables for the rest of the address space. The result of this is on context switch, at most we just have to update the CR3 register to the incoming thread's PDPT. The x86_mmu_api test was making too many assumptions and has been adjusted to work with the new design. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> |
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| CMakeLists.txt | ||
| prj.conf | ||
| testcase.yaml | ||