167 lines
5.4 KiB
C
167 lines
5.4 KiB
C
/*
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* Copyright (c) 2018 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ARC_IOT_SYSCONF_H_
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#define _ARC_IOT_SYSCONF_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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typedef struct sysconf_reg {
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volatile uint32_t reserved1; /* 0x0 */
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volatile uint32_t AHBCLKDIV; /* AHB clock divisor */
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volatile uint32_t APBCLKDIV; /* APB clock divisor */
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volatile uint32_t APBCLKEN; /* APB module clock enable */
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volatile uint32_t CLKODIV; /* AHB clock output enable and divisor set */
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volatile uint32_t reserved2; /* 0x14 */
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volatile uint32_t RSTCON; /* reset contrl */
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volatile uint32_t RSTSTAT; /* reset status */
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volatile uint32_t AHBCLKDIV_SEL; /* AHB clock divisor select */
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volatile uint32_t CLKSEL; /* main clock source select */
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volatile uint32_t PLLSTAT; /* PLL status register */
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volatile uint32_t PLLCON; /* PLL control register */
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volatile uint32_t reserved3; /* 0x30 */
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volatile uint32_t AHBCLKEN; /* AHB module clock enbale */
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volatile uint32_t reserved4[2]; /* 0x38, 0x3c */
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volatile uint32_t I2S_TX_SCLKDIV; /* I2S TX SCLK divisor */
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volatile uint32_t I2S_RX_SCLKDIV; /* I2S RX SCLK divisor */
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volatile uint32_t I2S_RX_SCLKSEL; /* I2S RX SCLK source select */
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volatile uint32_t SDIO_REFCLK_DIV; /* SDIO reference clock divisor */
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volatile uint32_t GPIO4B_DBCLK_DIV; /* GPIO4B DBCLK divisor */
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volatile uint32_t IMAGE_CHK; /* Image pad status */
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volatile uint32_t PROT_RANGE; /* PROT range */
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volatile uint32_t SPI_MST_CLKDIV; /* SPI master clock divisor */
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volatile uint32_t DVFS_CLKDIV; /* DFSS main clock domain divider */
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volatile uint32_t DVFS_VDDSET; /* VDD setting */
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volatile uint32_t DVFS_VWTIME; /* VDD adjust waiting time */
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volatile uint32_t PMC_PUWTIME; /* power up waiting time */
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volatile uint32_t PMOD_MUX; /* PMOD IO mux */
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volatile uint32_t ARDUINO_MUX; /* arduino IO mux */
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volatile uint32_t USBPHY_PLL; /* USBPHY PLL */
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volatile uint32_t USBCFG; /* USB configuration */
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volatile uint32_t TIMER_PAUSE; /* PWM timer puse */
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volatile uint32_t GPIO8B_DBCLK_DIV; /* GPIO8B DBCLK divisor */
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volatile uint32_t RESET_PD_VECTOR; /* reset powerdown vector */
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volatile uint32_t UART3SCLK_DIV; /* UART3SCLK_DIV */
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} sysconf_reg_t;
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/* CLKSEL_CONST is not described in spec. */
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#define CLKSEL_CONST (0x5A690000)
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#define CLKSEL_EXT_16M (0 | CLKSEL_CONST)
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#define CLKSEL_PLL (1 | CLKSEL_CONST)
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#define CLKSEL_EXT_32K (2 | CLKSEL_CONST)
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#define PLLCON_BIT_OFFSET_N 0
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#define PLLCON_BIT_OFFSET_M 4
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#define PLLCON_BIT_OFFSET_OD 20
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#define PLLCON_BIT_OFFSET_BP 24
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#define PLLCON_BIT_OFFSET_PLLRST 26
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#define PLLSTAT_BIT_OFFSET_PLLSTB 2
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#define PLLSTAT_BIT_OFFSET_PLLRDY 3
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#define AHBCLKEN_BIT_I2S 0
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#define AHBCLKEN_BIT_USB 1
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#define AHBCLKEN_BIT_FLASH 2
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#define AHBCLKEN_BIT_FMC 3
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#define AHBCLKEN_BIT_DVFS 4
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#define AHBCLKEN_BIT_PMC 5
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#define AHBCLKEN_BIT_BOOT_SPI 6
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#define AHBCLKEN_BIT_SDIO 7
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#define APBCLKEN_BIT_ADC 0
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#define APBCLKEN_BIT_I2S_TX 1
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#define APBCLKEN_BIT_I2S_RX 2
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#define APBCLKEN_BIT_RTC 3
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#define APBCLKEN_BIT_PWM 4
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#define APBCLKEN_BIT_I3C 5
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#define SPI_MASTER_0 0
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#define SPI_MASTER_1 1
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#define SPI_MASTER_2 2
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#define GPIO8B_BANK0 0
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#define GPIO8B_BANK1 1
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#define GPIO8B_BANK2 2
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#define GPIO8B_BANK3 3
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#define GPIO4B_BANK0 0
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#define GPIO4B_BANK1 1
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#define GPIO4B_BANK2 2
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/* reset caused by power on */
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#define SYS_RST_SOFTWARE_ON 0x2
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#define DVFS_PERF_LEVEL0 0
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#define DVFS_PERF_LEVEL1 1
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#define DVFS_PERF_LEVEL2 2
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#define DVFS_PERF_LEVEL3 3
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/* pmode mux definition */
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#define PMOD_MUX_PMA (0x1)
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#define PMOD_MUX_PMB (0x2)
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#define PMOD_MUX_PMC (0x4)
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/* arduino mux definition */
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#define ARDUINO_MUX_UART (0x1)
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#define ARDUINO_MUX_SPI (0x2)
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#define ARDUINO_MUX_PWM0 (0x4)
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#define ARDUINO_MUX_PWM1 (0x8)
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#define ARDUINO_MUX_PWM2 (0x10)
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#define ARDUINO_MUX_PWM3 (0x20)
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#define ARDUINO_MUX_PWM4 (0x40)
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#define ARDUINO_MUX_PWM5 (0x80)
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#define ARDUINO_MUX_I2C (0x100)
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#define ARDUINO_MUX_ADC0 (0x400)
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#define ARDUINO_MUX_ADC1 (0x800)
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#define ARDUINO_MUX_ADC2 (0x1000)
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#define ARDUINO_MUX_ADC3 (0x2000)
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#define ARDUINO_MUX_ADC4 (0x4000)
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#define ARDUINO_MUX_ADC5 (0x8000)
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#define PWM_TIMER0 0
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#define PWM_TIMER1 1
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#define PWM_TIMER2 2
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#define PWM_TIMER3 3
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#define PWM_TIMER4 4
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#define PWM_TIMER5 5
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extern void arc_iot_pll_conf_reg(uint32_t val);
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extern int32_t arc_iot_pll_fout_config(uint32_t freq);
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extern void arc_iot_ahb_clk_divisor(uint8_t div);
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extern void arc_iot_ahb_clk_enable(uint8_t dev);
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extern void arc_iot_ahb_clk_disable(uint8_t dev);
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extern void arc_iot_sdio_clk_divisor(uint8_t div);
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extern void arc_iot_spi_master_clk_divisor(uint8_t id, uint8_t div);
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extern void arc_iot_gpio8b_dbclk_div(uint8_t bank, uint8_t div);
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extern void arc_iot_gpio4b_dbclk_div(uint8_t bank, uint8_t div);
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extern void arc_iot_i2s_tx_clk_div(uint8_t div);
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extern void arc_iot_i2s_rx_clk_div(uint8_t div);
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extern void arc_iot_i2s_rx_clk_sel(uint8_t sel);
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extern void arc_iot_syscon_reset(void);
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extern uint32_t arc_iot_is_poweron_rst(void);
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extern void arc_iot_dvfs_clk_divisor(uint8_t level, uint8_t div);
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extern void arc_iot_dvfs_vdd_config(uint8_t level, uint8_t val);
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extern void arc_iot_dvfs_vwtime_config(uint8_t time);
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extern void arc_iot_pmc_pwwtime_config(uint8_t time);
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extern void arc_iot_uart3_clk_divisor(uint8_t div);
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extern void arc_iot_reset_powerdown_vector(uint32_t addr);
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extern void arc_iot_eflash_clk_div(uint8_t div);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ARC_IOT_SYSCONF_H_ */ |