Filip Kokosinski 8388bb7c24 soc: riscv: sifive-freedom: fix SYS_CLOCK_HW_CYCLES_PER_SEC value ... This commit fixes the default value of SYS_CLOCK_HW_CYCLES_PER_SEC option. The previous value of 32768 is not consistent with the documentation of FE310 SoC. Only FE310-based boards rely on the default value of this option; other boards from the Freedom series define it themselves. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>		2022-03-24 10:46:34 +01:00
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esp32c3	everywhere: fix typos	2022-03-18 13:24:08 -04:00
litex-vexriscv	…
openisa_rv32m1	everywhere: fix typos	2022-03-18 13:24:08 -04:00
riscv-ite	ITE drivers/interrupt_controller: add wuc interface	2022-03-21 16:35:03 -07:00
riscv-privilege	soc: riscv: sifive-freedom: fix SYS_CLOCK_HW_CYCLES_PER_SEC value	2022-03-24 10:46:34 +01:00
CMakeLists.txt	…