311 lines
8.4 KiB
C
311 lines
8.4 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_kinetis_dspi
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#include <errno.h>
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#include <drivers/spi.h>
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#include <drivers/clock_control.h>
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#include <fsl_dspi.h>
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(spi_mcux_dspi);
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#include "spi_context.h"
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struct spi_mcux_config {
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SPI_Type *base;
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char *clock_name;
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clock_control_subsys_t clock_subsys;
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void (*irq_config_func)(struct device *dev);
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};
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struct spi_mcux_data {
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dspi_master_handle_t handle;
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struct spi_context ctx;
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size_t transfer_len;
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};
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static int spi_mcux_transfer_next_packet(struct device *dev)
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{
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const struct spi_mcux_config *config = dev->config_info;
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struct spi_mcux_data *data = dev->driver_data;
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SPI_Type *base = config->base;
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struct spi_context *ctx = &data->ctx;
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dspi_transfer_t transfer;
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status_t status;
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if ((ctx->tx_len == 0) && (ctx->rx_len == 0)) {
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/* nothing left to rx or tx, we're done! */
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spi_context_cs_control(&data->ctx, false);
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spi_context_complete(&data->ctx, 0);
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return 0;
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}
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transfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcsContinuous |
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(ctx->config->slave << DSPI_MASTER_PCS_SHIFT);
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if (ctx->tx_len == 0) {
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/* rx only, nothing to tx */
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transfer.txData = NULL;
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transfer.rxData = ctx->rx_buf;
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transfer.dataSize = ctx->rx_len;
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} else if (ctx->rx_len == 0) {
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/* tx only, nothing to rx */
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transfer.txData = (uint8_t *) ctx->tx_buf;
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transfer.rxData = NULL;
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transfer.dataSize = ctx->tx_len;
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} else if (ctx->tx_len == ctx->rx_len) {
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/* rx and tx are the same length */
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transfer.txData = (uint8_t *) ctx->tx_buf;
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transfer.rxData = ctx->rx_buf;
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transfer.dataSize = ctx->tx_len;
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} else if (ctx->tx_len > ctx->rx_len) {
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/* Break up the tx into multiple transfers so we don't have to
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* rx into a longer intermediate buffer. Leave chip select
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* active between transfers.
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*/
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transfer.txData = (uint8_t *) ctx->tx_buf;
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transfer.rxData = ctx->rx_buf;
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transfer.dataSize = ctx->rx_len;
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transfer.configFlags |= kDSPI_MasterActiveAfterTransfer;
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} else {
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/* Break up the rx into multiple transfers so we don't have to
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* tx from a longer intermediate buffer. Leave chip select
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* active between transfers.
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*/
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transfer.txData = (uint8_t *) ctx->tx_buf;
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transfer.rxData = ctx->rx_buf;
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transfer.dataSize = ctx->tx_len;
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transfer.configFlags |= kDSPI_MasterActiveAfterTransfer;
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}
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if (!(ctx->tx_count <= 1 && ctx->rx_count <= 1)) {
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transfer.configFlags |= kDSPI_MasterActiveAfterTransfer;
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}
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data->transfer_len = transfer.dataSize;
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status = DSPI_MasterTransferNonBlocking(base, &data->handle, &transfer);
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if (status != kStatus_Success) {
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LOG_ERR("Transfer could not start");
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}
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return status == kStatus_Success ? 0 :
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status == kDSPI_Busy ? -EBUSY : -EINVAL;
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}
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static void spi_mcux_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct spi_mcux_config *config = dev->config_info;
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struct spi_mcux_data *data = dev->driver_data;
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SPI_Type *base = config->base;
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DSPI_MasterTransferHandleIRQ(base, &data->handle);
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}
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static void spi_mcux_master_transfer_callback(SPI_Type *base,
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dspi_master_handle_t *handle, status_t status, void *userData)
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{
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struct device *dev = userData;
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struct spi_mcux_data *data = dev->driver_data;
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spi_context_update_tx(&data->ctx, 1, data->transfer_len);
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spi_context_update_rx(&data->ctx, 1, data->transfer_len);
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spi_mcux_transfer_next_packet(dev);
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}
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static int spi_mcux_configure(struct device *dev,
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const struct spi_config *spi_cfg)
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{
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const struct spi_mcux_config *config = dev->config_info;
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struct spi_mcux_data *data = dev->driver_data;
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SPI_Type *base = config->base;
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dspi_master_config_t master_config;
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struct device *clock_dev;
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uint32_t clock_freq;
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uint32_t word_size;
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if (spi_context_configured(&data->ctx, spi_cfg)) {
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/* This configuration is already in use */
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return 0;
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}
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DSPI_MasterGetDefaultConfig(&master_config);
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if (spi_cfg->slave > FSL_FEATURE_DSPI_CHIP_SELECT_COUNT) {
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LOG_ERR("Slave %d is greater than %d",
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spi_cfg->slave, FSL_FEATURE_DSPI_CHIP_SELECT_COUNT);
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return -EINVAL;
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}
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word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
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if (word_size > FSL_FEATURE_DSPI_MAX_DATA_WIDTH) {
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LOG_ERR("Word size %d is greater than %d",
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word_size, FSL_FEATURE_DSPI_MAX_DATA_WIDTH);
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return -EINVAL;
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}
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master_config.ctarConfig.bitsPerFrame = word_size;
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master_config.ctarConfig.cpol =
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(SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL)
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? kDSPI_ClockPolarityActiveLow
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: kDSPI_ClockPolarityActiveHigh;
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master_config.ctarConfig.cpha =
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(SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA)
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? kDSPI_ClockPhaseSecondEdge
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: kDSPI_ClockPhaseFirstEdge;
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master_config.ctarConfig.direction =
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(spi_cfg->operation & SPI_TRANSFER_LSB)
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? kDSPI_LsbFirst
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: kDSPI_MsbFirst;
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master_config.ctarConfig.baudRate = spi_cfg->frequency;
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clock_dev = device_get_binding(config->clock_name);
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if (clock_dev == NULL) {
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return -EINVAL;
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}
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if (clock_control_get_rate(clock_dev, config->clock_subsys,
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&clock_freq)) {
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return -EINVAL;
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}
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DSPI_MasterInit(base, &master_config, clock_freq);
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DSPI_MasterTransferCreateHandle(base, &data->handle,
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spi_mcux_master_transfer_callback, dev);
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DSPI_SetDummyData(base, 0);
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data->ctx.config = spi_cfg;
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spi_context_cs_configure(&data->ctx);
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return 0;
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}
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static int transceive(struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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bool asynchronous,
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struct k_poll_signal *signal)
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{
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struct spi_mcux_data *data = dev->driver_data;
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int ret;
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spi_context_lock(&data->ctx, asynchronous, signal);
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ret = spi_mcux_configure(dev, spi_cfg);
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if (ret) {
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goto out;
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}
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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spi_context_cs_control(&data->ctx, true);
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ret = spi_mcux_transfer_next_packet(dev);
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if (ret) {
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goto out;
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}
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ret = spi_context_wait_for_completion(&data->ctx);
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out:
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spi_context_release(&data->ctx, ret);
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return ret;
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}
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static int spi_mcux_transceive(struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL);
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}
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#ifdef CONFIG_SPI_ASYNC
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static int spi_mcux_transceive_async(struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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struct k_poll_signal *async)
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{
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, async);
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}
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#endif /* CONFIG_SPI_ASYNC */
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static int spi_mcux_release(struct device *dev,
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const struct spi_config *spi_cfg)
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{
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struct spi_mcux_data *data = dev->driver_data;
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static int spi_mcux_init(struct device *dev)
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{
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const struct spi_mcux_config *config = dev->config_info;
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struct spi_mcux_data *data = dev->driver_data;
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config->irq_config_func(dev);
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static const struct spi_driver_api spi_mcux_driver_api = {
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.transceive = spi_mcux_transceive,
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#ifdef CONFIG_SPI_ASYNC
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.transceive_async = spi_mcux_transceive_async,
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#endif
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.release = spi_mcux_release,
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};
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#define SPI_MCUX_DSPI_DEVICE(id) \
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static void spi_mcux_config_func_##id(struct device *dev); \
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static const struct spi_mcux_config spi_mcux_config_##id = { \
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.base = (SPI_Type *)DT_INST_REG_ADDR(id), \
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.clock_name = DT_INST_CLOCKS_LABEL(id), \
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.clock_subsys = \
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(clock_control_subsys_t)DT_INST_CLOCKS_CELL(id, name), \
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.irq_config_func = spi_mcux_config_func_##id, \
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}; \
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static struct spi_mcux_data spi_mcux_data_##id = { \
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SPI_CONTEXT_INIT_LOCK(spi_mcux_data_##id, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_mcux_data_##id, ctx), \
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}; \
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DEVICE_AND_API_INIT(spi_mcux_##id, \
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DT_INST_LABEL(id), \
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&spi_mcux_init, \
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&spi_mcux_data_##id, \
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&spi_mcux_config_##id, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&spi_mcux_driver_api); \
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static void spi_mcux_config_func_##id(struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(id), \
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DT_INST_IRQ(id, priority), \
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spi_mcux_isr, DEVICE_GET(spi_mcux_##id), \
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0); \
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irq_enable(DT_INST_IRQN(id)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(SPI_MCUX_DSPI_DEVICE)
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