275 lines
6.5 KiB
Plaintext
275 lines
6.5 KiB
Plaintext
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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* Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>
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* Copyright (c) 2018 Foundries.io Ltd
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*
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* This file is based on:
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*
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* - include/arch/arm/cortex_m/scripts/linker.ld
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* - include/arch/riscv/common/linker.ld
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* - include/arch/riscv/pulpino/linker.ld
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-tool.h>
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/*
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* Extra efforts would need to be taken to ensure the IRQ handlers are within
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* jumping distance of the vector table in non-XIP builds, so avoid them.
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*/
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#define ROMABLE_REGION ROM
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#define RAMABLE_REGION RAM
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#define VECTOR_SIZE 0x100
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#ifdef CONFIG_USE_DT_CODE_PARTITION
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_code_partition)))
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#define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_code_partition)))
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#define VECTOR_BASE (ROM_BASE + CONFIG_ROM_START_OFFSET)
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#else
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#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_code_partition)))
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#define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_code_partition)) - VECTOR_BASE)
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#define VECTOR_BASE (ROM_BASE + ROM_SIZE)
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#endif
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#else
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#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
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#define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) - VECTOR_SIZE)
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#define VECTOR_BASE (ROM_BASE + ROM_SIZE)
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#endif
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#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define RAM_SIZE KB(CONFIG_SRAM_SIZE)
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MEMORY
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{
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ROM (rx) : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
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/*
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* Each RISC-V core on this chip (RI5CY and ZERO-RISCY) has
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* a vector table at the end of its flash bank. They are relocatable
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* at runtime, but we need to put the reset vectors in hardcoded places.
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*
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* (The Arm core vector tables are at the beginning of each
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* flash bank.)
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*/
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#ifndef CONFIG_BOOTLOADER_MCUBOOT
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VECTORS (rx) : ORIGIN = VECTOR_BASE, LENGTH = VECTOR_SIZE
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#endif
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RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
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/*
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* Special section, not included in the final binary, used
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* to generate interrupt tables. See include/linker/intlist.ld.
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*/
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IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
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}
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ENTRY(CONFIG_KERNEL_ENTRY)
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SECTIONS
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{
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#include <zephyr/linker/rel-sections.ld>
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#ifdef CONFIG_LLEXT
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#include <zephyr/linker/llext-sections.ld>
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#endif
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SECTION_PROLOGUE(.plt,,)
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{
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*(.plt)
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}
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SECTION_PROLOGUE(.iplt,,)
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{
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*(.iplt)
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}
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GROUP_START(ROM)
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__rom_region_start = ROM_BASE;
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SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
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{
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/* Located in generated directory. This file is populated by calling
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* zephyr_linker_sources(ROM_START ...). This typically contains the vector
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* table and debug information.
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*/
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#include <snippets-rom-start.ld>
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__text_region_start = .;
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*(.text .text.*)
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*(.gnu.linkonce.t.*)
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*(.eh_frame)
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} GROUP_LINK_IN(ROM)
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__text_region_end = .;
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__rodata_region_start = .;
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#include <zephyr/linker/common-rom.ld>
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/* Located in generated directory. This file is populated by calling
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* zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs.
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*/
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#include <snippets-rom-sections.ld>
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#include <zephyr/linker/thread-local-storage.ld>
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
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*(.srodata)
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*(".srodata.*")
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.r.*)
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-rodata.ld>
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} GROUP_LINK_IN(ROMABLE_REGION)
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#include <zephyr/linker/cplusplus-rom.ld>
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__rodata_region_end = .;
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__rom_region_end = .;
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#ifndef CONFIG_BOOTLOADER_MCUBOOT
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/* The vector table goes into core-dependent flash locations. */
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SECTION_PROLOGUE(vectors,,)
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{
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_vector_start = .;
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KEEP(*(.vectors.*))
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} GROUP_LINK_IN(VECTORS)
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_vector_end = .;
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#endif
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GROUP_END(ROM)
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GROUP_START(RAM)
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SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
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_image_ram_start = .;
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__data_region_start = .;
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__data_start = .;
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.s.*)
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/* https://groups.google.com/a/groups.riscv.org/d/msg/sw-dev/60IdaZj27dY/TKT3hbNlAgAJ */
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*(.sdata .sdata.* .gnu.linkonce.s.*)
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*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-rwdata.ld>
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__data_end = .;
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
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__data_size = __data_end - __data_start;
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__data_load_start = LOADADDR(_DATA_SECTION_NAME);
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#include <zephyr/linker/common-ram.ld>
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#include <zephyr/linker/cplusplus-ram.ld>
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-data-sections.ld>
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__data_region_end = .;
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__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);
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SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
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{
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/*
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* For performance, BSS section is assumed to be 4 byte aligned and
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* a multiple of 4 bytes, so it can be cleared in words.
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*/
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. = ALIGN(4);
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__bss_start = .;
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*(.bss .bss.*)
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*(.sbss .sbss.*)
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COMMON_SYMBOLS
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/* Ensure 4 byte alignment for the entire section. */
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. = ALIGN(4);
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__bss_end = .;
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
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{
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/*
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* This section is used for non-initialized objects that
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* will not be cleared during the boot process.
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*/
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*(.noinit .noinit.*)
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-noinit.ld>
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} GROUP_LINK_IN(RAMABLE_REGION)
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-ram-sections.ld>
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-sections.ld>
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#include <zephyr/linker/ram-end.ld>
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GROUP_END(RAMABLE_REGION)
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#ifdef CONFIG_GEN_ISR_TABLES
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/* Bogus section, post-processed during the build to initialize interrupts. */
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#include <zephyr/linker/intlist.ld>
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#endif
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#include <zephyr/linker/debug-sections.ld>
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SECTION_PROLOGUE(.riscv.attributes, 0,)
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{
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KEEP(*(.riscv.attributes))
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KEEP(*(.gnu.attributes))
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}
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/*
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* Pulpino toolchains emit these sections; we don't care about them,
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* but need to avoid build system warnings about orphaned sections.
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*/
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SECTION_PROLOGUE(.Pulp_Chip.Info,,)
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{
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*(.Pulp_Chip.*)
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}
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}
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