40 lines
1.9 KiB
C
40 lines
1.9 KiB
C
/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef SOC_ARM_NORDIC_NRF_NRF54H_SOC_H_
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#define SOC_ARM_NORDIC_NRF_NRF54H_SOC_H_
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#include <soc_nrf_common.h>
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#if defined(CONFIG_SOC_NRF54H20_CPUAPP) || defined(CONFIG_SOC_NRF54H20_ENGB_CPUAPP)
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#define RAMBLOCK_CONTROL_BIT_ICACHE MEMCONF_POWER_CONTROL_MEM1_Pos
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#define RAMBLOCK_CONTROL_BIT_DCACHE MEMCONF_POWER_CONTROL_MEM2_Pos
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#define RAMBLOCK_POWER_ID 0
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#define RAMBLOCK_CONTROL_OFF 0
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#define RAMBLOCK_RET_MASK (MEMCONF_POWER_RET_MEM0_Msk)
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#define RAMBLOCK_RET_BIT_ICACHE MEMCONF_POWER_RET_MEM1_Pos
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#define RAMBLOCK_RET_BIT_DCACHE MEMCONF_POWER_RET_MEM2_Pos
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#elif defined(CONFIG_SOC_NRF54H20_CPURAD) || defined(CONFIG_SOC_NRF54H20_ENGB_CPURAD)
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#define RAMBLOCK_CONTROL_BIT_ICACHE MEMCONF_POWER_CONTROL_MEM6_Pos
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#define RAMBLOCK_CONTROL_BIT_DCACHE MEMCONF_POWER_CONTROL_MEM7_Pos
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#define RAMBLOCK_POWER_ID 0
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#define RAMBLOCK_CONTROL_OFF 0
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#define RAMBLOCK_RET_MASK \
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(MEMCONF_POWER_RET_MEM0_Msk | MEMCONF_POWER_RET_MEM1_Msk | MEMCONF_POWER_RET_MEM2_Msk | \
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MEMCONF_POWER_RET_MEM3_Msk | MEMCONF_POWER_RET_MEM4_Msk | MEMCONF_POWER_RET_MEM5_Msk | \
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MEMCONF_POWER_RET_MEM8_Msk)
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#define RAMBLOCK_RET2_MASK \
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(MEMCONF_POWER_RET2_MEM0_Msk | MEMCONF_POWER_RET2_MEM1_Msk | MEMCONF_POWER_RET2_MEM2_Msk | \
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MEMCONF_POWER_RET2_MEM3_Msk | MEMCONF_POWER_RET2_MEM4_Msk | MEMCONF_POWER_RET2_MEM5_Msk | \
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MEMCONF_POWER_RET2_MEM8_Msk)
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#define RAMBLOCK_RET_BIT_ICACHE MEMCONF_POWER_RET_MEM6_Pos
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#define RAMBLOCK_RET_BIT_DCACHE MEMCONF_POWER_RET_MEM7_Pos
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#define RAMBLOCK_RET2_BIT_ICACHE MEMCONF_POWER_RET2_MEM6_Pos
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#define RAMBLOCK_RET2_BIT_DCACHE MEMCONF_POWER_RET2_MEM7_Pos
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#endif
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#endif /* SOC_ARM_NORDIC_NRF_NRF54H_SOC_H_ */
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